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M58LT128HSB8ZA6E 参数 Datasheet PDF下载

M58LT128HSB8ZA6E图片预览
型号: M58LT128HSB8ZA6E
PDF下载: 下载PDF文件 查看货源
内容描述: 128兆位(8 MB 】 16 ,多银行,多接口,突发) 1.8 V电源供电,安全闪存 [128 Mbit (8 Mb 】16, multiple bank, multilevel interface, burst) 1.8 V supply, secure Flash memories]
分类和应用: 闪存存储内存集成电路
文件页数/大小: 110 页 / 2025 K
品牌: NUMONYX [ NUMONYX B.V ]
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Common Flash Interface  
M58LT128HST, M58LT128HSB  
Description Value  
Table 36. Protection Register information  
Offset  
Data  
Number of Protection Register fields in JEDEC ID space.  
0000h indicates that 256 fields are available.  
(P+E)h = 118h  
(P+F)h = 119h  
0002h  
2
0080h Protection Field 1: Protection description  
Bits 0-7 Lower byte of Protection Register address  
80h  
00h  
8 bytes  
8 bytes  
89h  
00h  
00h  
00h  
0
(P+10)h = 11Ah 0000h  
(P+ 11)h = 11Bh 0003h  
(P+12)h = 11Ch 0003h  
(P+13)h = 11Dh 0089h  
(P+14)h = 11Eh 0000h  
(P+15)h = 11Fh 0000h  
(P+16)h = 120h 0000h  
(P+17)h = 121h 0000h  
(P+18)h = 122h 0000h  
(P+19)h = 123h 0000h  
(P+1A)h = 124h 0010h  
(P+1B)h = 125h 0000h  
(P+1C)h = 126h 0004h  
Bits 8-15 Upper byte of Protection Register address  
Bits 16-23 2n bytes in factory preprogrammed region  
Bits 24-31 2n bytes in user-programmable region  
Protection Register 2: protection description  
Bits 0-31 Protection Register address  
Bits 32-39 n number of factory programmed regions (lower  
byte)  
Bits 40-47 n number of factory programmed regions (upper  
byte)  
Bits 48-55 2n bytes in factory programmable region  
0
Bits 56-63 n number of user programmable regions (lower  
byte)  
0
16  
Bits 64-71 n number of user programmable regions (upper  
byte)  
Bits 72-79 2n bytes in user programmable region  
0
16  
Table 37. Burst Read information  
Offset Data  
Description  
Page-mode read capability  
Value  
bits 0-7 n’ such that 2n HEX value represents the number of  
read-page bytes. See offset 0028h for device word width to  
determine page-mode data output width.  
(P+1D)h = 127h 0003h  
(P+1E)h = 128h 0004h  
8 bytes  
Number of Synchronous mode read configuration fields that  
follow.  
4
4
Synchronous mode read capability configuration 1  
bit 3-7 Reserved  
bit 0-2 n’ such that 2n+1 HEX value represents the maximum  
number of continuous synchronous reads when the device is  
configured for its maximum word width. A value of 07h  
indicates that the device is capable of continuous linear  
bursts that output data until the internal burst counter  
reaches the end of the device’s burstable address space.  
This field’s 3-bit value can be written directly to the read  
Configuration Register bit 0-2 if the device is configured for  
its maximum word width. See offset 0028h for word width to  
determine the burst data output width.  
(P+1F)h = 129h 0001h  
(P+20)h = 12Ah 0002h Synchronous mode read capability configuration 2  
8
Synchronous mode read capability configuration 3  
Synchronous mode read capability configuration 4  
16  
(P-21)h = 12Bh 0003h  
(P+22)h = 12Ch 0007h  
Cont.  
86/110  
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