M58LT128HST, M58LT128HSB
Common Flash Interface
Table 40. Bank and Erase Block region 2 Information
M58LT128HSB
(bottom)
M58LT128HST (top)
Offset Data
Description
Offset
Data
(P+32)h = 13Ch 01h (P+3A)h = 144h 0Fh
(P+33)h = 13Dh 00h (P+3B)h = 145h 00h
Number of identical banks within bank region 2
Number of Program or Erase operations allowed
in bank region 2:
Bits 0-3: Number of simultaneous Program
operations
(P+34)h = 13Eh 11h (P+3C)h = 146h 11h
Bits 4-7: Number of simultaneous Erase
operations
Number of Program or Erase operations allowed
in other banks while a bank in this region is
programming
(P+35)h = 13Fh 00h (P+3D)h = 147h 00h Bits 0-3: Number of simultaneous Program
operations
Bits 4-7: Number of simultaneous Erase
operations
Number of Program or Erase operations allowed
in other banks while a bank in this region is
erasing
(P+36)h = 140h 00h (P+3E)h = 148h 00h Bits 0-3: Number of simultaneous Program
operations
Bits 4-7: Number of simultaneous Erase
operations
Types of Erase Block regions in Bank Region 2
n = number of Erase Block regions with
(P+37)h = 141h 02h (P+3F)h = 149h 01h contiguous same-size erase blocks.
Symmetrically blocked banks have one blocking
region.(2)
(P+38)h = 142h 06h (P+40)h = 14Ah 07h
(P+39)h = 143h 00h (P+41)h = 14Bh 00h
(P+3A)h = 144h 00h (P+42)h = 14Ch 00h
(P+3B)h = 145h 02h (P+43)h = 14Dh 02h
(P+3C)h = 146h 64h (P+44)h = 14Eh 64h
(P+3D)h = 147h 00h (P+45)h = 14Fh 00h
Bank region 2 Erase Block type 1 Information
Bits 0-15: n+1 = number of same-size erase
blocks
Bits 16-31: n×256 = number of bytes in Erase
Block region
Bank region 2 (Erase Block type 1)
Minimum Block Erase cycles × 1000
Bank region 2 (Erase Block type 1): BIts per cell,
internal ECC
Bits 0-3: bits per cell in Erase region
Bit 4: reserved for “internal ECC used”
BIts 5-7: reserved
(P+3E)h = 148h 01h (P+46)h = 150h 01h
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NUMONYX [ NUMONYX B.V ]
