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M58LT128HSB8ZA6E 参数 Datasheet PDF下载

M58LT128HSB8ZA6E图片预览
型号: M58LT128HSB8ZA6E
PDF下载: 下载PDF文件 查看货源
内容描述: 128兆位(8 MB 】 16 ,多银行,多接口,突发) 1.8 V电源供电,安全闪存 [128 Mbit (8 Mb 】16, multiple bank, multilevel interface, burst) 1.8 V supply, secure Flash memories]
分类和应用: 闪存存储内存集成电路
文件页数/大小: 110 页 / 2025 K
品牌: NUMONYX [ NUMONYX B.V ]
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DC and AC parameters  
M58LT128HST, M58LT128HSB  
(1)  
Table 24. Write AC characteristics, Write Enable controlled  
M58LT128HST/B Unit  
85  
Symbol  
Alt  
Parameter  
tAVAV  
tAVLH  
tWC Address Valid to Next Address Valid  
Address Valid to Latch Enable High  
Address Valid to Write Enable High  
tDS Data Valid to Write Enable High  
Chip Enable Low to Latch Enable High  
tCS Chip Enable Low to Write Enable Low  
Chip Enable Low to Output Valid  
Min  
Min  
Min  
Min  
Min  
Min  
Min  
Min  
Min  
Min  
Min  
Min  
Min  
Min  
Min  
Min  
Min  
Min  
Min  
Min  
Min  
Min  
85  
10  
50  
50  
10  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
(2)  
tAVWH  
tDVWH  
tELLH  
tELWL  
tELQV  
tELKV  
tGHWL  
tLHAX  
tLLLH  
85  
9
Chip Enable Low to Clock Valid  
Output Enable High to Write Enable Low  
Latch Enable High to Address Transition  
Latch Enable Pulse Width  
17  
9
10  
0
(2)  
tWHAV  
Write Enable High to Address Valid  
tAH Write Enable High to Address Transition  
tDH Write Enable High to Input Transition  
tCH Write Enable High to Chip Enable High  
Write Enable High to Chip Enable Low  
Write Enable High to Output Enable Low  
Write Enable High to Latch Enable Low  
(2)  
tWHAX  
tWHDX  
tWHEH  
0
0
0
(3)  
tWHEL  
tWHGL  
25  
0
(3)  
tWHLL  
25  
25  
50  
0
tWHWL tWPH Write Enable High to Write Enable Low  
tWLWH  
tQVVPL  
tWP Write Enable Low to Write Enable High  
Output (Status Register) Valid to VPP Low  
tVPHWH tVPS VPP High to Write Enable High  
200  
tWHVPL  
Write Enable High to VPP Low  
Min  
200  
ns  
1. Sampled only, not 100% tested.  
2. Meaningful only if L is always kept low.  
3. tWHEL and tWHLL have this value when reading in the targeted bank or when reading following a Set  
Configuration Register command. System designers should take this into account and may insert a  
software No-Op instruction to delay the first read in the same bank after issuing any command and to delay  
the first read to any address after issuing a Set Configuration Register command. If the first read after the  
command is a Read Array operation in a different bank and no changes to the Configuration Register have  
been issued, tWHEL and tWHLL are 0 ns.  
66/110  
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