欢迎访问ic37.com |
会员登录 免费注册
发布采购

M58LT128HSB8ZA6E 参数 Datasheet PDF下载

M58LT128HSB8ZA6E图片预览
型号: M58LT128HSB8ZA6E
PDF下载: 下载PDF文件 查看货源
内容描述: 128兆位(8 MB 】 16 ,多银行,多接口,突发) 1.8 V电源供电,安全闪存 [128 Mbit (8 Mb 】16, multiple bank, multilevel interface, burst) 1.8 V supply, secure Flash memories]
分类和应用: 闪存存储内存集成电路
文件页数/大小: 110 页 / 2025 K
品牌: NUMONYX [ NUMONYX B.V ]
 浏览型号M58LT128HSB8ZA6E的Datasheet PDF文件第19页浏览型号M58LT128HSB8ZA6E的Datasheet PDF文件第20页浏览型号M58LT128HSB8ZA6E的Datasheet PDF文件第21页浏览型号M58LT128HSB8ZA6E的Datasheet PDF文件第22页浏览型号M58LT128HSB8ZA6E的Datasheet PDF文件第24页浏览型号M58LT128HSB8ZA6E的Datasheet PDF文件第25页浏览型号M58LT128HSB8ZA6E的Datasheet PDF文件第26页浏览型号M58LT128HSB8ZA6E的Datasheet PDF文件第27页  
M58LT128HST, M58LT128HSB  
Command interface  
4.9  
Buffer Program command  
The Buffer Program Command makes use of the device’s 32-word Write Buffer to accelerate  
programming. Up to 32 words can be loaded into the Write Buffer, which can dramatically  
reduce in-system programming time compared to the standard non-buffered Program  
command.  
Four successive steps are required to issue the Buffer Program command:  
1. The first Bus Write cycle sets up the Buffer Program command. The setup code can be  
addressed to any location within the targeted block.  
After the first Bus Write cycle, Read operations in the bank output the contents of the Status  
Register. Status Register bit SR7 should be read to check that the buffer is available (SR7 =  
‘1’). If the buffer is not available (SR7 = ‘0’), re-issue the Buffer Program command to update  
the Status Register contents.  
2. The second Bus Write cycle sets up the number of words to be programmed. Value ”n”  
is written to the same block address, where n+1 is the number of words to be  
programmed.  
3. Use n+1 Bus Write cycles to load the address and data for each word into the Write  
Buffer. Addresses must lie within the range from the start address to the start address  
+ n, where the start address is the location of the first data to be programmed.  
Optimum performance is obtained when the start address corresponds to a 32-word  
boundary.  
4. The final Bus Write cycle confirms the Buffer Program command and starts the  
program operation.  
All the addresses used in the Buffer Program operation must lie within the same block.  
Invalid address combinations or an incorrect sequence of Bus Write cycles sets an error in  
the Status Register and aborts the operation without affecting the data in the memory array.  
If the block being programmed is protected an error is set in the Status Register, and the  
operation aborts without affecting the data in the memory array.  
During Buffer Program operations the bank being programmed only accepts the Read Array,  
Read Status Register, Read Electronic Signature, Read CFI Query, and the Program/Erase  
Suspend command; all other commands are ignored.  
Refer to Chapter 8: Dual operations and multiple bank architecture for detailed information  
about simultaneous operations allowed in banks not being programmed.  
See Appendix C, Figure 21: Buffer Program flowchart and pseudo code for a suggested  
flowchart on using the Buffer Program command.  
23/110  
 复制成功!