M58LT128HST, M58LT128HSB
Command interface
4.10.2
Program and verify phase
The program and verify phase requires 32 cycles to program the 32 words to the Write
Buffer. The data is stored sequentially, starting at the first address of the Write Buffer, until
the Write Buffer is full (32 words). To program less than 32 words, the remaining words
should be programmed with FFFFh.
The following three successive steps are required to issue and execute the program and
verify phase of the command.
1. Use one Bus Write operation to latch the Start Address and the first word to be
programmed. The Status Register Bank Write status bit SR0 should be read to check
that the Program/Erase Controller is ready for the next word.
2. Each subsequent word to be programmed is latched with a new Bus Write operation.
The address must remain the start address as the Program/Erase Controller
increments the address location. If any address is given that is not in the same block as
the start address, the program and verify phase terminates. Status Register bit SR0
should be read between each Bus Write cycle to check that the Program/Erase
Controller is ready for the next word.
3. Once the Write Buffer is full, the data is programmed sequentially to the memory array.
After the Program operation, the device automatically verifies the data and reprograms,
if necessary.
The program and verify phase can be repeated, without re-issuing the command, to
program additional 32 word locations as long as the address remains in the same block.
4. Finally, after all words, or the entire block has been programmed, write one Bus Write
operation to any address outside the block containing the start address, to terminate
program and verify phase.
Status Register bit SR0 must be checked to determine whether the Program operation is
finished. The Status Register may be checked for errors at any time but it must be checked
after the entire block has been programmed.
4.10.3
Exit phase
Status Register Program/Erase Controller bit SR7 set to ‘1’ indicates that the device has
exited the Buffer Enhanced Factory Program operation and returned to Read Status
Register mode. A full Status Register check should be done to ensure that the block has
been successfully programmed. See Section Table 5: Status Register for more details.
For optimum performance the Buffer Enhanced Factory Program command should be
limited to a maximum of 100 program/erase cycles per block. If this limit is exceeded, the
internal algorithm continues to work properly but some degradation in performance is
possible. Typical program times are given in Table 16.
See Appendix C, Figure 27: Buffer Enhanced Factory Program flowchart and pseudo code
for a suggested flowchart on using the Buffer Enhanced Factory Program command.
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