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M25PE80-VMN6P 参数 Datasheet PDF下载

M25PE80-VMN6P图片预览
型号: M25PE80-VMN6P
PDF下载: 下载PDF文件 查看货源
内容描述: 8兆位,页擦除串行闪存与字节变性, 75兆赫的SPI总线,标准引脚 [8-Mbit, page-erasable serial flash memory with byte alterability, 75 MHz SPI bus, standard pinout]
分类和应用: 闪存内存集成电路
文件页数/大小: 66 页 / 1387 K
品牌: NUMONYX [ NUMONYX B.V ]
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M25PE80  
Instructions  
6.4  
Read status register (RDSR)  
The Read Status Register (RDSR) instruction allows the status register to be read. The  
status register may be read at any time, even while a program, erase or write cycle is in  
progress. When one of these cycles is in progress, it is recommended to check the write in  
progress (WIP) bit before sending a new instruction to the device. It is also possible to read  
the status register continuously, as shown in Figure 10.  
The status bits of the status register are as follows:  
6.4.1  
6.4.2  
6.4.3  
WIP bit  
The write in progress (WIP) bit indicates whether the memory is busy with a write, program  
or erase cycle. When set to ‘1’, such a cycle is in progress, when reset to ‘0’ no such cycle is  
in progress.  
WEL bit  
The write enable latch (WEL) bit indicates the status of the internal Write Enable Latch.  
When set to ‘1’ the internal Write Enable Latch is set, when set to ‘0’ the internal Write  
Enable Latch is reset and no write, program or erase instruction is accepted.  
BP2, BP1, BP0 bits  
The block protect (BP2, BP1, BP0) bits are non-volatile. They define the size of the area to  
be software protected against program and erase instructions. These bits are written with  
the write status register (WRSR) instruction. When one or more of the block protect (BP2,  
BP1, BP0) bits is set to ‘1’, the relevant memory area (as defined in Table 4) becomes  
protected against Page Program (PP), Sector Erase (SE) and SubSector Erase (SSE)  
instructions. The block protect (BP2, BP1, BP0) bits can be written provided that the  
hardware protected mode has not been set. The Bulk Erase (BE) instruction is executed if,  
and only if:  
all block protect (BP2, BP1, BP0) bits are 0  
the lock register protection bits are not all set (‘1’).  
6.4.4  
SRWD bit  
The status register write disable (SRWD) bit is operated in conjunction with the Write  
Protect (W) signal. When the status register write disable (SRWD) bit is set to ‘1’, and Write  
Protect (W) is driven Low, the non-volatile bits of the status register (SRWD, BP2, BP1, BP0)  
become read-only bits. In such a state, as the write status register (WRSR) instruction is no  
longer accepted for execution, the definition of the size of the write protected area cannot be  
further modified.  
(1) (2) (3)  
Table 8.  
Status register format  
b7  
b0  
SRWD  
0
0
BP2  
BP1  
BP0  
WEL  
WIP  
1. WEL (write enable latch) and WIP ((write in program) are volatile read-only bits (WEL is set and reset by  
specific instructions; WIP is automatically set and reset by the internal logic of the device).  
2. SRWD = status register write protect bit; BP0, BP1, BP2 = block protect bits.  
3. The BP bits and the SRWD bit exist only in the T9HX process.  
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