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M25PE80-VMN6P 参数 Datasheet PDF下载

M25PE80-VMN6P图片预览
型号: M25PE80-VMN6P
PDF下载: 下载PDF文件 查看货源
内容描述: 8兆位,页擦除串行闪存与字节变性, 75兆赫的SPI总线,标准引脚 [8-Mbit, page-erasable serial flash memory with byte alterability, 75 MHz SPI bus, standard pinout]
分类和应用: 闪存内存集成电路
文件页数/大小: 66 页 / 1387 K
品牌: NUMONYX [ NUMONYX B.V ]
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M25PE80  
Instructions  
6.6  
Read data bytes (READ)  
The device is first selected by driving Chip Select (S) Low. The instruction code for the Read  
data bytes (READ) instruction is followed by a 3-byte address (A23-A0), each bit being  
latched-in during the rising edge of Serial Clock (C). Then the memory contents, at that  
address, is shifted out on serial data output (Q), each bit being shifted out, at a maximum  
frequency f , during the falling edge of Serial Clock (C).  
R
The instruction sequence is shown in Figure 12.  
The first byte addressed can be at any location. The address is automatically incremented  
to the next higher address after each byte of data is shifted out. The whole memory can,  
therefore, be read with a single read data bytes (READ) instruction. When the highest  
address is reached, the address counter rolls over to 000000h, allowing the read sequence  
to be continued indefinitely.  
The read data bytes (READ) instruction is terminated by driving Chip Select (S) High. Chip  
Select (S) can be driven High at any time during data output. Any read data bytes (READ)  
instruction, while an erase, program or write cycle is in progress, is rejected without having  
any effects on the cycle that is in progress.  
Figure 12. Read data bytes (READ) instruction sequence and data-out sequence  
S
0
1
2
3
4
5
6
7
8
9
10  
28 29 30 31 32 33 34 35 36 37 38 39  
C
Instruction  
24-bit address  
23 22 21  
MSB  
3
2
1
0
D
Q
Data out 1  
Data out 2  
High Impedance  
2
7
6
5
4
3
1
7
0
MSB  
AI03748D  
1. Address bits A23 to A20 are don’t care.  
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