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M25P20-VMP3G/X 参数 Datasheet PDF下载

M25P20-VMP3G/X图片预览
型号: M25P20-VMP3G/X
PDF下载: 下载PDF文件 查看货源
内容描述: 2兆位,低电压,串行闪存与50MHz的SPI总线接口 [2 Mbit, low voltage, Serial Flash memory with 50MHz SPI bus interface]
分类和应用: 闪存
文件页数/大小: 50 页 / 964 K
品牌: NUMONYX [ NUMONYX B.V ]
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M25P20  
Instructions  
Table 4.  
Instruction Set  
Description  
One-byte Instruction Address Dummy Data  
Instruction  
Code  
Bytes  
Bytes  
Bytes  
WREN  
WRDI  
Write Enable  
0000 0110  
0000 0100  
1001 1111  
0000 0101  
0000 0001  
0000 0011  
06h  
04h  
9Fh  
05h  
01h  
03h  
0
0
0
0
0
3
0
0
0
0
0
0
0
Write Disable  
0
RDID(1)  
RDSR  
WRSR  
READ  
Read Identification  
Read Status Register  
Write Status Register  
Read Data Bytes  
1 to 3  
1 to ∞  
1
1 to ∞  
Read Data Bytes at Higher  
Speed  
FAST_READ  
0000 1011  
0Bh  
3
1
1 to ∞  
PP  
SE  
BE  
DP  
Page Program  
Sector Erase  
Bulk Erase  
0000 0010  
1101 1000  
1100 0111  
1011 1001  
02h  
D8h  
C7h  
B9h  
3
3
0
0
0
0
0
0
1 to 256  
0
0
0
Deep Power-down  
Release from Deep Power-  
down, and Read Electronic  
Signature  
0
0
3
0
1 to ∞  
RES  
1010 1011  
ABh  
Release from Deep Power-  
down  
0
1. The Read Identification (RDID) instruction is available only in products with Process Technology code X  
(see Application Note AN1995).  
6.1  
Write Enable (WREN)  
The Write Enable (WREN) instruction (Figure 7) sets the Write Enable Latch (WEL) bit.  
The Write Enable Latch (WEL) bit must be set prior to every Page Program (PP), Sector  
Erase (SE), Bulk Erase (BE) and Write Status Register (WRSR) instruction.  
The Write Enable (WREN) instruction is entered by driving Chip Select (S) Low, sending the  
instruction code, and then driving Chip Select (S) High.  
Figure 7.  
Write Enable (WREN) Instruction Sequence  
S
0
1
2
3
4
5
6
7
C
D
Q
Instruction  
High Impedance  
AI02281E  
17/50  
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