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M25P20-VMP3G/X 参数 Datasheet PDF下载

M25P20-VMP3G/X图片预览
型号: M25P20-VMP3G/X
PDF下载: 下载PDF文件 查看货源
内容描述: 2兆位,低电压,串行闪存与50MHz的SPI总线接口 [2 Mbit, low voltage, Serial Flash memory with 50MHz SPI bus interface]
分类和应用: 闪存
文件页数/大小: 50 页 / 964 K
品牌: NUMONYX [ NUMONYX B.V ]
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M25P20  
Operating features  
Table 2.  
Protected Area Sizes  
Status Register  
Content  
Memory Content  
BP1 Bit BP0 Bit  
Protected Area  
Unprotected Area  
0
0
0
1
none  
All sectors(1)(four sectors: 0, 1, 2 and 3)  
Lower three-quarters (three sectors: 0  
to 2)  
Upper quarter (Sector 3)  
1
1
0
1
Upper half (two sectors: 2 and 3)  
Lower half (Sectors 0 and 1)  
All sectors (four sectors: 0, 1, 2 and 3) none  
1. The device is ready to accept a Bulk Erase instruction if, and only if, both Block Protect (BP1, BP0) are 0.  
4.7  
Hold Condition  
The Hold (HOLD) signal is used to pause any serial communications with the device without  
resetting the clocking sequence. However, taking this signal Low does not terminate any  
Write Status Register, Program or Erase cycle that is currently in progress.  
To enter the Hold condition, the device must be selected, with Chip Select (S) Low.  
The Hold condition starts on the falling edge of the Hold (HOLD) signal, provided that this  
coincides with Serial Clock (C) being Low (as shown in Figure 5).  
The Hold condition ends on the rising edge of the Hold (HOLD) signal, provided that this  
coincides with Serial Clock (C) being Low.  
If the falling edge does not coincide with Serial Clock (C) being Low, the Hold condition  
starts after Serial Clock (C) next goes Low. Similarly, if the rising edge does not coincide  
with Serial Clock (C) being Low, the Hold condition ends after Serial Clock (C) next goes  
Low. (This is shown in Figure 5).  
During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data  
Input (D) and Serial Clock (C) are Don’t Care.  
Normally, the device is kept selected, with Chip Select (S) driven Low, for the whole duration  
of the Hold condition. This is to ensure that the state of the internal logic remains unchanged  
from the moment of entering the Hold condition.  
If Chip Select (S) goes High while the device is in the Hold condition, this has the effect of  
resetting the internal logic of the device. To restart communication with the device, it is  
necessary to drive Hold (HOLD) High, and then to drive Chip Select (S) Low. This prevents  
the device from going back to the Hold condition.  
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