M25P10-A
Power-up and power-down
7
Power-up and power-down
At power-up and power-down, the device must not be selected (that is Chip Select (S) must
follow the voltage applied on V ) until V reaches the correct value:
CC
CC
●
V
V
(min) at power-up, and then for a further delay of t
at power-down
CC
SS
VSL
●
A safe configuration is provided in Section 3: SPI modes.
To avoid data corruption and inadvertent write operations during power-up, a Power On
Reset (POR) circuit is included. The logic inside the device is held reset while V is less
CC
than the Power On Reset (POR) threshold voltage, V – all operations are disabled, and
WI
the device does not respond to any instruction.
Moreover, the device ignores all Write Enable (WREN), Page Program (PP), Sector Erase
(SE), Bulk Erase (BE) and Write Status Register (WRSR) instructions until a time delay of
t
has elapsed after the moment that V rises above the V threshold. However, the
PUW
CC WI
correct operation of the device is not guaranteed if, by this time, V is still below V (min).
CC
CC
No Write Status Register, Program or Erase instructions should be sent until the later of:
●
t
t
after V passed the V threshold
CC WI
PUW
VSL
●
after V passed the V (min) level
CC
CC
These values are specified in Table 8.
If the delay, t
, has elapsed, after V has risen above V (min), the device can be
VSL
CC
CC
selected for read instructions even if the t
delay is not yet fully elapsed.
PUW
At power-up, the device is in the following state:
●
●
●
The device is in the Standby mode (not the Deep Power-down mode).
The Write Enable Latch (WEL) bit is reset.
The Write In Progress (WIP) bit is reset.
Normal precautions must be taken for supply rail decoupling, to stabilize the V supply.
CC
Each device in a system should have the V rail decoupled by a suitable capacitor close to
CC
the package pins. (Generally, this capacitor is of the order of 0.1 µF).
At power-down, when V drops from the operating voltage, to below the Power On Reset
CC
(POR) threshold voltage, V , all operations are disabled and the device does not respond
WI
to any instruction (the designer needs to be aware that if a power-down occurs while a
Write, Program or Erase cycle is in progress, some data corruption can result).
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NUMONYX [ NUMONYX B.V ]
