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M25P10-AVMB6TP/Y 参数 Datasheet PDF下载

M25P10-AVMB6TP/Y图片预览
型号: M25P10-AVMB6TP/Y
PDF下载: 下载PDF文件 查看货源
内容描述: 1兆位,串行闪存, 50MHz的SPI总线接口 [1 Mbit, serial Flash memory, 50 MHz SPI bus interface]
分类和应用: 闪存存储内存集成电路时钟
文件页数/大小: 51 页 / 989 K
品牌: NUMONYX [ NUMONYX B.V ]
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M25P10-A  
Instructions  
6.10  
Bulk Erase (BE)  
The Bulk Erase (BE) instruction sets all bits to ‘1’ (FFh). Before it can be accepted, a Write  
Enable (WREN) instruction must previously have been executed. After the Write Enable  
(WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL).  
The Bulk Erase (BE) instruction is entered by driving Chip Select (S) Low, followed by the  
instruction code on Serial Data input (D). Chip Select (S) must be driven Low for the entire  
duration of the sequence.  
The instruction sequence is shown in Figure 16.  
Chip Select (S) must be driven High after the eighth bit of the instruction code has been  
latched in, otherwise the Bulk Erase instruction is not executed. As soon as Chip Select (S)  
is driven High, the self-timed Bulk Erase cycle (whose duration is t ) is initiated. While the  
BE  
Bulk Erase cycle is in progress, the Status Register may be read to check the value of the  
Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Bulk  
Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is  
completed, the Write Enable Latch (WEL) bit is reset.  
The Bulk Erase (BE) instruction is executed only if both Block Protect (BP1, BP0) bits are 0.  
The Bulk Erase (BE) instruction is ignored if one, or more, sectors are protected.  
Figure 16. Bulk Erase (BE) instruction sequence  
S
0
1
2
3
4
5
6
7
C
D
Instruction  
AI03752D  
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