M25P128
DC and AC parameters
Table 17. AC characteristics for 130 nm devices
Test conditions specified in Table 11 and Table 12
Symbol
Alt.
Parameter
Min. Typ.
Max.
Unit
Clock frequency for the following instructions:
FAST_READ, PP, SE, BE, WREN, WRDI,
RDID, RDSR, WRSR
fC
fR
fC
D.C.
50
20
MHz
Clock frequency for READ instructions
D.C.
9
MHz
ns
(1)
tCH
tCLH Clock High Time
tCLL Clock Low Time
(1)
tCL
9
ns
(2)
tCLCH
Clock Rise Time(3) (peak to peak)
0.1
0.1
5
V/ns
V/ns
ns
tCHCL
Clock Fall Time(3) (peak to peak)
tCSS S Active Setup Time (relative to C)
S Not Active Hold Time (relative to C)
tDSU Data In Setup Time
(2)
tSLCH
tCHSL
tDVCH
tCHDX
tCHSH
tSHCH
tSHSL
5
ns
2
ns
tDH
Data In Hold Time
5
ns
S Active Hold Time (relative to C)
S Not Active Setup Time (relative to C)
5
ns
5
ns
tCSH S Deselect Time
100
ns
(2)
tSHQZ
tDIS Output Disable Time
8
8
ns
tCLQV
tCLQX
tHLCH
tCHHH
tHHCH
tCHHL
tV
tHO Output Hold Time
HOLD Setup Time (relative to C)
Clock Low to Output Valid
ns
0
5
5
5
5
ns
ns
HOLD Hold Time (relative to C)
HOLD Setup Time (relative to C)
HOLD Hold Time (relative to C)
HOLD to Output Low-Z
ns
ns
ns
(2)
tHHQX
tLZ
8
8
ns
(2)
tHLQZ
tHZ
HOLD to Output High-Z
ns
(4)
tWHSL
Write Protect Setup Time
Write Protect Hold Time
20
ns
(4)
tSHWL
100
ns
Enhanced Program Supply Voltage High to
Chip Select Low
(2)(5)
tVPPHSL
tW
200
ns
Write Status Register Cycle Time
Page Program Cycle Time (256 Bytes)
Page Program Cycle Time (n Bytes)
5
15
7
ms
2.5
2.5
(6)
tPP
ms
s
Page Program Cycle Time (VPP = VPPH) (256
Bytes)
1.2(2)
Sector Erase Cycle Time
2
tSE
6
Sector Erase Cycle Time (VPP = VPPH
)
1.6(2)
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