28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
9.3
Power Supply Decoupling
Flash memory power-switching characteristics require careful device decoupling. System
designers must consider the following three supply current issues:
1. Standby current levels (I
).
CCS
2. Read current levels (I
).
CCR
3. Transient peaks produced by falling and rising edges of CE#.
Transient current magnitudes depend on the device output capacitive and inductive loading.
Two-line control and proper decoupling capacitor selection suppresses these transient voltage
peaks. Each flash device must have a 0.1 µF ceramic capacitor connected between each V and
CC
GND, and between its V and GND. These high-frequency, inherently low-inductance capacitors
PP
must be placed as close as possible to the package leads.
9.4
Power Consumption
Intel® flash memory devices use a tiered approach to power savings that can significantly reduce
overall system power consumption. The Automatic Power Savings (APS) feature reduces power
consumption when the flash memory device is selected but idle. If CE# is deasserted, the flash
memory device enters its standby mode, where current consumption is even lower. The
combination of these features can minimize memory power consumption, and therefore minimize
overall system power consumption.
9.4.1
9.4.2
9.4.3
Active Power
When CE# is at a logic-low level and RP# is at a logic-high level, the flash memory device is in the
active mode. Refer to the DC Characteristic tables for I current values. Active power is the
largest contributor to overall system power consumption. Minimizing the active current can
profoundly affect system power consumption, especially for battery-operated devices.
CC
Automatic Power Savings (APS)
Automatic Power Savings provides low-power operation during read mode. After data is read from
the flash memory array and the address lines are quiescent, APS circuitry places the flash memory
device in a mode where typical current is comparable to I
state with outputs valid until a new location is read.
. The flash memory stays in this static
CCS
Standby Power
When CE# is at a logic-high level (V ) and the flash memory device is in read mode, the flash
IH
memory is in standby mode. This mode disables much of the device circuitry, and substantially
reduces power consumption. Outputs are placed in a high-impedance state independent of the
status of the OE# signal. If CE# transitions to a logic-high level during Erase or Program
operations, the flash memory device continues to perform the operation and consume
corresponding active power until the operation is completed.
System engineers must analyze the breakdown of standby time versus active time and quantify the
respective power consumption in each mode for their specific application. This approach provides
a more accurate measure of application-specific power and energy requirements.
Datasheet
Intel® Advanced Boot Block Flash Memory (B3)
Order Number: 290580, Revision: 020
18 Aug 2005
49
NUMONYX [ NUMONYX B.V ]
