Numonyx™ Wireless Flash Memory (W18)
Figure 23: Normal Write and Read Cycles
Address [A]
WE# [W]
OE# [G]
Data [Q]
Partition A
Partition A
Partition A
20h
Block Erase Setup
D0h
Block Erase Conf irm
FFh
Read Array
Figure 24: Interleaving a 2-Cycle Write Sequence with an Array Read
Address [A]
WE# [W]
OE# [G]
Data [Q]
Partition B
Partition A
Partition B
Partition A
FFh
Read Array
20h
Erase Setup
Array Data
Bus Read
D0h
Erase Conf irm
By contrast, a write bus cycle may not interrupt a 2-cycle write sequence. Doing so
causes a command sequence error to appear in the Status Register.
illustrates a command sequence error.
Figure 25: Improper Command Sequencing
Address [A]
WE# [W]
OE# [G]
Data [D/Q]
Partition X
Partitio n Y
Partition X
Partition X
20h
FFh
D0h
SR Data
Datasheet
54
November 2007
Order Number: 290701-18
NUMONYX [ NUMONYX B.V ]
