Typical Application Circuits
The typical application circuit used for SSTL-2 termination
schemes with DDR-SDRAM can be seen in Figure 5.
20039306
SSTL-2 Implementation
FIGURE 5.
For SSTL-3 and other applications it may be desirable to
*
set the output VTT to be equal to VDDQ 0.5. The addition
*
change internal reference voltage scaling from VDDQ 0.5.
of a 11.1 kΩ external resistor will change the internal refer-
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An external resistor in series with the VDDQ pin can be used
ence voltage causing the two outputs to track VDDQ 0.45.
to lower the reference voltage. Internally two 50 kΩ resistors
An implementation of this circuit can be seen in Figure 6.
20039307
SSTL-3 Implementation
FIGURE 6.
Another application that is sometimes required is to increase
resistor divider network between VTT, VSENSE and Ground.
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the VTT output voltage from the scaling factor of VDDQ 0.5.
An example of this circuit can be seen in Figure 7.
This can be accomplished independently of VREF by using a
20039303
FIGURE 7.
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