the DAP the θJA can be lowered significantly. Figure 3 shows
the LLP thermal data when placed on a 4-layer JEDEC
board with copper thickness of 0.5/1/1/0.5 oz. The number of
vias, with a pitch of 1.27 mm, has been increased to the
maximum of 4 where a θJA of 50.41˚C/W can be obtained.
Via wall thickness for this calculation is 0.036 mm for 1oz.
Copper.
Component Selection (Continued)
the best solution when size and performance are critical,
although their cost is typically higher than any other capaci-
tor.
Capacitor recommendations for different application circuits
can be seen in the accompanying application notes with
supporting evaluation boards.
Thermal Dissipation
Since the LP2995 is a linear regulator any current flow from
VTT will result in internal power dissipation generating heat.
To prevent damaging the part from exceeding the maximum
allowable junction temperature, care should be taken to
derate the part dependent on the maximum expected ambi-
ent temperature and power dissipation. The maximum allow-
able internal temperature rise (TRmax) can be calculated
given the maximum ambient temperature (TAmax) of the
application and the maximum allowable junction temperature
(TJmax).
TRmax = TJmax − TAmax
From this equation, the maximum power dissipation (PDmax
)
of the part can be calculated:
PDmax = TRmax / θJA
The θJA of the LP2995 will be dependent on several vari-
ables: the package used; the thickness of copper; the num-
ber of vias and the airflow. For instance, the θJA of the SO-8
is 163˚C/W with the package mounted to a standard 8x4
2-layer board with 1oz. copper, no airflow, and 0.5W dissi-
pation at room temperature. This value can be reduced to
151.2˚C/W by changing to a 3x4 board with 2 oz. copper that
is the JEDEC standard. Figure 2 shows how the θJA varies
with airflow for the two boards mentioned.
20039322
#
LLP-16 θJA vs of Vias (4 Layer JEDEC Board))
FIGURE 3.
Additional improvements in lowering the θJA can also be
achieved with a constant airflow across the package. Main-
taining the same conditions as above and utilizing the 2x2
via array, Figure 4 shows how the θJA varies with airflow.
20039321
20039323
θJA vs Airflow (SO-8)
θJA vs Airflow Speed (JEDEC Board with 4 Vias)
FIGURE 2.
FIGURE 4.
Layout is also extremely critical to maximize the output
current with the LLP package. By simply placing vias under
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