center of the termination bus.
PCB Layout Considerations
4. VDDQ can be connected remotely to the VDDQ rail
input at either the DIMM or the Chipset. This provides
the most accurate point for creating the reference volt-
age.
1. AVIN and PVIN should be tied together for optimal per-
formance. A local bypass capacitor should be placed as
close as possible to the PVIN pin.
2. GND should be connected to a ground plane with mul-
tiple vias for improved thermal performance.
5. VREF should be bypassed with a 0.01 µF or 0.1 µF
ceramic capacitor for improved performance. This ca-
pacitor should be located as close as possible to the
VREF pin.
3. VSENSE should be connected to the VTT termination bus
at the point where regulation is required. For mother-
board applications an ideal location would be at the
www.national.com
10
NSC [ National Semiconductor ]
