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LM80CIMT-3 参数 Datasheet PDF下载

LM80CIMT-3图片预览
型号: LM80CIMT-3
PDF下载: 下载PDF文件 查看货源
内容描述: 串行接口ACPI兼容微处理器系统硬件监控 [Serial Interface ACPI-Compatible Microprocessor System Hardware Monitor]
分类和应用: 微处理器光电二极管监控
文件页数/大小: 29 页 / 438 K
品牌: NSC [ National Semiconductor ]
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Functional Description (Continued)  
12.4 Interrupt Status Register 1 — Address 01h  
=
>
<
Power on default 7:0  
0000 0000 binary  
Bit  
0
Name  
IN0  
Read/Write  
Read Only  
Read Only  
Read Only  
Read Only  
Read Only  
Read Only  
Read Only  
Read Only  
Description  
A one indicates a High or Low limit has been exceeded.  
A one indicates a High or Low limit has been exceeded.  
A one indicates a High or Low limit has been exceeded.  
A one indicates a High or Low limit has been exceeded.  
A one indicates a High or Low limit has been exceeded.  
A one indicates a High or Low limit has been exceeded.  
A one indicates a High or Low limit has been exceeded.  
A zero indicates that a Low has been detected on the INT_IN.  
1
IN1  
2
IN2  
3
IN3  
4
IN4  
5
IN5  
6
IN6  
7
INT_IN  
12.5 Interrupt Status Register 2 — Address 02h  
=
>
<
Power on default 7:0  
0000 0000 binary  
Bit  
Name  
Read/Write  
Description  
0
1
Hot Temperature  
Read Only  
A one indicates a High or Low limit has been exceeded. Only “One-Time Interrupt”  
and “Default Interrupt” modes are supported. The mode is set by bit-6 of the  
Interrupt Mask Register 2.  
BTI  
Read Only  
A one indicates that an interrupt has occurred from the Board Temperature  
Interrupt (BTI) input pin. BTI can be tied to the OS output of multiple LM75 chips.  
2
3
4
FAN1  
FAN2  
Read Only  
Read Only  
Read Only  
A one indicates that a fan count limit has been exceeded.  
A one indicates that a fan count limit has been exceeded.  
A one indicates CI (Chassis Intrusion) has gone high.  
CI (Chassis  
Intrusion)  
5
OS bit  
Read Only  
A one indicates a High or a Low OS Temperature limit has been exceed. Only  
comparator mode is supported. Only “One-Time Interrupt” and “Default Interrupt”  
modes are supported. The mode is set by bit-7 of the Interrupt Mask Register 2.  
6
7
Reserved  
Reserved  
Read Only  
Read Only  
12.6 Interrupt Mask Register 1 — Address 03h  
=
>
<
Power on default 7:0  
Bit Name  
IN0  
0000 0000 binary  
Read/  
Description  
Write  
0
1
2
3
4
5
6
7
Read/Write  
Read/Write  
Read/Write  
Read/Write  
Read/Write  
Read/Write  
Read/Write  
Read/Write  
A one disables the corresponding interrupt status bit for INT interrupt.  
A one disables the corresponding interrupt status bit for INT interrupt.  
A one disables the corresponding interrupt status bit for INT interrupt.  
A one disables the corresponding interrupt status bit for INT interrupt.  
A one disables the corresponding interrupt status bit for INT interrupt.  
A one disables the corresponding interrupt status bit for INT interrupt.  
A one disables the corresponding interrupt status bit for INT interrupt.  
A one disables the corresponding interrupt status bit for INT interrupt.  
IN1  
IN2  
IN3  
IN4  
IN5  
IN6  
INT_IN  
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