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LM80CIMT-3 参数 Datasheet PDF下载

LM80CIMT-3图片预览
型号: LM80CIMT-3
PDF下载: 下载PDF文件 查看货源
内容描述: 串行接口ACPI兼容微处理器系统硬件监控 [Serial Interface ACPI-Compatible Microprocessor System Hardware Monitor]
分类和应用: 微处理器光电二极管监控
文件页数/大小: 29 页 / 438 K
品牌: NSC [ National Semiconductor ]
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Functional Description (Continued)  
12.3 Configuration Register — Address 00h  
=
>
<
Power on default 7:0  
Bit Name  
Start  
00001000 binary  
Read/  
Write  
Description  
0
Read/Write  
A one enables startup of monitoring operations, a zero puts the part in standby mode.  
Note: The outputs of Interrupt pins will not be cleared if the user writes a zero to this  
location after an interrupt has occurred unlike “INT_Clear” bit.At start up, limit checking  
functions and scanning begin. Note, all limits should be set in the Value RAM before  
setting this bit HIGH.  
1
2
INT Enable  
Read/Write  
Read/Write  
A one enables the INT Interrupt output.  
INT polarity  
select  
A one selects an active high open source output while a zero selects an active low  
open drain output.  
3
4
5
INT_Clear  
Read/Write  
Read/Write  
Read/Write  
A one disables the INT and RST_OUT/OS outputs without affecting the contents of  
Interrupt Status Registers. The device will stop monitoring. It will resume upon clearing  
of this bit.  
=
< >  
7
RESET  
A one outputs at least a 10 ms active low reset signal at RESET, if  
1 and  
=
< >  
6
0 in the Fan Divisor/RST_OUT/OS Register. This bit is cleared once the pulse  
has gone inactive.  
Chassis Clear  
A one clears the CI (Chassis Intrusion) pin. This bit clears itself after the CI pins  
cleared.  
6
7
GPO  
Read/Write  
Read/Write  
A one in this bit drives a one on GPO (General Purpose Output) pin.  
INITIALIZATION  
A one restores power on default value to the Configuration Register, Interrupt Status  
Registers, Interrupt Mask Registers, Fan Divisor/RST_OUT/OSRegister, and the OS  
Configuration/Temperature Resolution Register. This bit clears itself since the power  
on default is zero.  
23  
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