CON, Panasonic SP CAP, Nichicon "NA" series, are also
recommended and may be used without additional series re-
sistance.
Design Information
Hysteretic control is a simple control scheme. However the
operating frequency and other performance characteristics
highly depend on external conditions and components. If ei-
ther the inductance, output capacitance, ESR, VIN, or Cff is
changed, there will be a change in the operating frequency
and output ripple. The best approach is to determine what
operating frequency is desirable in the application and then
begin with the selection of the inductor and COUT ESR.
For all practical purposes, any type of output capacitor may
be used with proper circuit verification.
INPUT CAPACITOR SELECTION (CIN)
A bypass capacitor is required between the input source and
ground. It must be located near the source pin of the external
PFET. The input capacitor prevents large voltage transients
at the input and provides the instantaneous current when the
PFET turns on.
INDUCTOR SELECTION (L1)
The important parameters for the inductor are the inductance
and the current rating. The LM3485 operates over a wide fre-
quency range and can use a wide range of inductance values.
A good rule of thumb is to use the equations used for
National's Simple Switchers®. The equation for inductor rip-
ple (Δi) as a function of output current (IOUT) is:
The important parameters for the input capacitor are the volt-
age rating and the RMS current rating. Follow the
manufacturer's recommended voltage derating. For high in-
put voltage application, low ESR electrolytic capacitor, the
Nichicon "UD" series or the Panasonic "FK" series, is avail-
able. The RMS current in the input capacitor can be calculat-
ed.
for Iout < 2.0Amps
−0.366726
ꢀΔi ≤ Iout * 0.386827 * Iout
for Iout > 2.0Amps
ꢀΔi ≤ Iout * 0.3
The inductance can be calculated based upon the desired
operating frequency where:
The input capacitor power dissipation can be calculated as
follows.
PD(CIN) = IRMS_CIN2 * ESRCIN
The input capacitor must be able to handle the RMS current
and the PD. Several input capacitors may be connected in
parallel to handle large RMS currents. In some cases it may
be much cheaper to use multiple electrolytic capacitors than
a single low ESR, high performance capacitor such as OS-
CON or Tantalum. The capacitance value should be selected
such that the ripple voltage created by the charge and dis-
charge of the capacitance is less than 10% of the total ripple
across the capacitor.
And
where D is the duty cycle, VD is the diode forward voltage, and
VDS is the voltgae drop across the PFET.
PROGRAMMING THE CURRENT LIMIT (RADJ
)
The inductor should be rated to the following:
The current limit is determined by connecting a resistor
(RADJ) between input voltage and the ADJ pin.
Ipk = (Iout+Δi/2)*1.1
RADJ = IIND_PEAK * RDSON/ICL_ADJ
where:
RDSON : Drain-Source ON resistance of the external PFET
ICL_ADJ : 3.0µA minimum
The inductance value and the resulting ripple is one of the key
parameters controlling operating frequency. The second is
the ESR.
IIND_PEAK = ILOAD + IRIPPLE/2
Using the minimum value for ICL_ADJ (3.0µA) ensures that the
current limit threshold will be set higher than the peak inductor
current.
OUTPUT CAPACITOR SELECTION (COUT
)
The ESR of the output capacitor times the inductor ripple cur-
rent is equal to the output ripple of the regulator. However, the
VHYST sets the first order value of this ripple. As ESR is in-
creased with a given inductance, then operating frequency
increases as well. If ESR is reduced then the operating fre-
quency reduces.
The RADJ value must be selected to ensure that the voltage
at the ADJ pin does not fall below 3.5V. With this in mind,
RADJ_MAX = (VIN-3.5)/7µA. If a larger RADJ value is needed to
set the desired current limit, either use a PFET with a lower
RDSON, or use a current sense resistor as shown in Figure 5.
The current limit function can be disabled by connecting the
ADJ pin to ground and ISENSE to VIN.
The use of ceramic capacitors has become a common desire
of many power supply designers. However, ceramic capaci-
tors have a very low ESR resulting in a 90° phase shift of the
output voltage ripple. This results in low operating frequency
and increased output ripple. To fix this problem a low value
resistor should be added in series with the ceramic output
capacitor. Although counter intuitive, this combination of a
ceramic capacitor and external series resistance provide
highly accurate control over the output voltage ripple. The
other types capacitor, such as Sanyo POS CAP and OS-
CATCH DIODE SELECTION (D1)
The important parameters for the catch diode are the peak
current, the peak reverse voltage, and the average power
dissipation. The average current through the diode can be
calculated as following.
ID_AVE = IOUT* (1 − D)
11
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