will not be accidentally triggered. A value of 100pF to 1nF is
recommended in most applications. Higher values can be
used to create a soft-start function (See Start Up section).
an RC time constant forcing current limit to activate at a lower
current. The output voltage will ramp more slowly when using
the soft-start functionality. There are example start-up plots
for CADJ equal to 1nF and 10nF in the Typical Performance
Characteristics. Lower values for CADJ will have little to no
effect on soft-start.
The current limit comparator has approximately 100ns of
blanking time. This ensures that the PFET is fully on when the
current is sensed. However, under extreme conditions such
as cold temperature, some PFETs may not fully turn on within
the blanking time. In this case, the current limit threshold must
be increased. If the current limit function is used, the on time
must be greater than 100ns. Under low duty cycle operation,
the maximum operating frequency will be limited by this min-
imum on time.
EXTERNAL SENSE RESISTOR
The VDS of a PFET will tend to vary significantly over temper-
ature. This will result an equivalent variation in current limit.
To improve current limit accuracy an external sense resistor
can be connected from VIN to the source of the PFET, as
shown in Figure 5.
During current limit operation, the output voltage will drop sig-
nificantly as will operating frequency. As the load current is
reduced, the output will return to the programmed voltage.
However, there is a current limit fold back phenomenon in-
herent in this current limit architecture. See Figure 4.
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FIGURE 5. Current Sensing by External Resistor
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PGATE
FIGURE 4. Current Limit Fold Back Phenomenon
When switching, the PGATE pin swings from VIN (off) to
some voltage below VIN (on). How far the PGATE will swing
depends on several factors including the capacitance, on
time, and input voltage.
At high input voltages (>28V) increased undershoot at the
switch node can cause an increase in the current limit thresh-
old. To avoid this problem, a low Vf Schottky catch diode must
be used (See Catch Diode Selection). Additionally, a resistor
can be placed between the ISENSE pin and the switch node.
Any value up to approximately 600Ω is recommended.
As shown in the Typical Performance Characteristics,
PGATE voltage swing will increase with decreasing gate ca-
pacitance. Although PGATE voltage will typically be around
VIN-5V, with every small gate capacitances, this value can
increase to a typical maximum of VIN-8.3V.
START UP
The current limit circuit is active during start-up. During start-
up the PFET will stay on until either the current limit or the
feedback comparator is tripped
Additionally, PGATE swing voltage will increase as on time
increases. During long on times, such as when operating at
100% duty cycle, the PGATE voltage will eventually fall to its
maximum voltage of VIN-8.3V (typical) regardless of the
PFET gate capacitance.
If the current limit comparator is tripped first then the fold back
characteristic should be taken into account. Start-up into full
load may require a higher current limit set point or the load
must be applied after start-up.
The PGATE voltage will not fall below 0.4V (typical). There-
fore, when the input voltage falls below approximately 9V, the
PGATE swing voltage range will be reduced. At an input volt-
age of 7V, for instance, PGATE will swing from 7V to a
minimum of 0.4V.
One problem with selecting a higher current limit is inrush
current during start-up. Increasing the capacitance (CADJ) in
parallel with RADJ results in soft-start. CADJ and RADJ create
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