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DS90CR215MTD 参数 Datasheet PDF下载

DS90CR215MTD图片预览
型号: DS90CR215MTD
PDF下载: 下载PDF文件 查看货源
内容描述: + 3.3V上升沿数据选通LVDS 21位通道链接 - 66 MHz的 [+3.3V Rising Edge Data Strobe LVDS 21-Bit Channel Link - 66 MHz]
分类和应用: 线路驱动器或接收器驱动程序和接口接口集成电路光电二极管
文件页数/大小: 17 页 / 736 K
品牌: NSC [ NATIONAL SEMICONDUCTOR ]
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DS90CR215/DS90CR216
Transmitter Switching Characteristics
Symbol
TPPos3
TPPos4
TPPos5
TPPos6
TPPos0
TPPos1
TPPos2
TPPos3
TPPos4
TPPos5
TPPos6
TCIP
TCIH
TCIL
TSTC
THTC
TCCD
TPLLS
TPDD
Parameter
Transmitter Output Pulse Position for Bit3
Transmitter Output Pulse Position for Bit4
Transmitter Output Pulse Position for Bit5
Transmitter Output Pulse Position for Bit6
Transmitter Output Pulse Position for Bit0
Transmitter Output Pulse Position for Bit1
Transmitter Output Pulse Position for Bit2
Transmitter Output Pulse Position for Bit3
Transmitter Output Pulse Position for Bit4
Transmitter Output Pulse Position for Bit5
Transmitter Output Pulse Position for Bit6
TxCLK IN Period (Figure
TxCLK IN High Time (Figure
TxCLK IN Low Time (Figure
TxIN Setup to TxCLK IN (Figure
TxIN Hold to TxCLK IN (Figure
(Continued)
Over recommended operating supply and −40˚C to +85˚C ranges unless otherwise specified
Min
10.2
13.7
17.3
21.0
f = 66 MHz
−0.4
1.8
4.0
6.2
8.4
10.6
12.8
15
0.35T
0.35T
2.5
0
3
3.7
5.5
10
100
Typ
10.4
13.9
17.6
21.2
0
2.2
4.4
6.6
8.8
11.0
13.2
T
0.5T
0.5T
Max
11.0
14.6
18.2
21.8
0.3
2.5
4.7
6.9
9.1
11.3
13.5
50
0.65T
0.65T
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
TxCLK IN to TxCLK OUT Delay
@
25˚C,V
CC
=3.3V (Figure
Transmitter Phase Lock Loop Set (Figure
Transmitter Powerdown Delay (Figure
Receiver Switching Characteristics
Over recommended operating supply and −40˚C to +85˚C ranges unless otherwise specified
Symbol
CLHT
CHLT
RSPos0
RSPos1
RSPos2
RSPos3
RSPos4
RSPos5
RSPos6
RSPos0
RSPos1
RSPos2
RSPos3
RSPos4
RSPos5
RSPos6
RSKM
RCOP
RCOH
RCOL
Parameter
CMOS/TTL Low-to-High Transition Time (Figure
CMOS/TTL High-to-Low Transition Time (Figure
Receiver Input Strobe Position for Bit 0 (Note 7)(Figure
Receiver Input Strobe Position for Bit 1
Receiver Input Strobe Position for Bit 2
Receiver Input Strobe Position for Bit 3
Receiver Input Strobe Position for Bit 4
Receiver Input Strobe Position for Bit 5
Receiver Input Strobe Position for Bit 6
Receiver Input Strobe Position for Bit 0 (Note 6)(Figure
Receiver Input Strobe Position for Bit 1
Receiver Input Strobe Position for Bit 2
Receiver Input Strobe Position for Bit 3
Receiver Input Strobe Position for Bit 4
Receiver Input Strobe Position for Bit 5
Receiver Input Strobe Position for Bit 6
RxIN Skew Margin (Note 5) (Figure
RxCLK OUT Period (Figure
RxCLK OUT High Time (Figure
RxCLK OUT Low Time (Figure
f = 40 MHz
f = 66 MHz
f = 40 MHz
f = 66 MHz
f = 40 MHz
f = 66 MHz
f = 66 MHz
f = 40 MHz
1.0
4.5
8.1
11.6
15.1
18.8
22.5
0.7
2.9
5.1
7.3
9.5
11.7
13.9
490
400
15
6.0
4.0
10.0
6.0
T
10.0
6.1
13.0
7.8
50
Min
Typ
2.2
2.2
1.4
5.0
8.5
11.9
15.6
19.2
22.9
1.1
3.3
5.5
7.7
9.9
12.1
14.3
Max
5.0
5.0
2.15
5.8
9.15
12.6
16.3
19.9
23.6
1.4
3.6
5.8
8.0
10.2
12.4
14.6
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
ps
ns
ns
ns
ns
ns
5
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