DS90CR215/DS90CR216
Receiver Switching Characteristics
Symbol
RSRC
RHRC
RCCD
RPLLS
RPDD
Parameter
RxOUT Setup to RxCLK OUT (Figure
RxOUT Hold to RxCLK OUT (Figure
RxCLK IN to RxCLK OUT Delay (Figure
Receiver Phase Lock Loop Set (Figure
Receiver Powerdown Delay (Figure
(Continued)
Over recommended operating supply and −40˚C to +85˚C ranges unless otherwise specified
Min
f = 40 MHz
f = 66 MHz
f = 40 MHz
f = 66 MHz
f = 40 MHz
f = 66 MHz
6.5
2.5
6.0
2.5
4.0
5.0
Typ
14.0
8.0
8.0
4.0
6.7
6.6
8.0
9.0
10
1
Max
Units
ns
ns
ns
ns
ns
ns
ms
µs
Note 5:
Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account for transmitter pulse positions (min
and max) and the receiver input setup and hold time (internal data sampling window). This margin allows LVDS interconnect skew, inter-symbol interference (both
dependent on type/length of cable), and clock jitter less than 250 ps.
Note 6:
The min. and max. limits are based on the worst bit by applying a −400ps/+300ps shift from ideal position.
Note 7:
The min. and max. are based on the actual bit position of each of the 7 bits within the LVDS data stream across PVT.
AC Timing Diagrams
01290902
FIGURE 1. “Worst Case” Test Pattern
01290903
01290904
FIGURE 2. DS90CR215 (Transmitter) LVDS Output Load and Transition Times
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