DS90CR215/DS90CR216
AC Timing Diagrams
(Continued)
01290920
C — Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and max
Tppos — Transmitter output pulse position (min and max)
RSKM
≥
Cable Skew (type, length) + Source Clock Jitter (cycle to cycle) (Note 11) + ISI (Inter-symbol interference) (Note 12)
Cable Skew — typicaIIy 10 ps–40 ps per foot, media dependent
Note 11:
Cycle-to-cycle jitter is less than 250 ps
Note 12:
ISI is dependent on interconnect length; may be zero
FIGURE 18. Receiver LVDS Input Skew Margin
Applications Information
The DS90CR215 and DS90CR216 are backward compatible
with the existing 5V Channel Link transmitter/receiver pair
(DS90CR213, DS90CR214). To upgrade from a 5V to a 3.3V
system the following must be addressed:
1. Change 5V power supply to 3.3V. Provide this supply to
the V
CC
, LVDS V
CC
and PLL V
CC
.
Transmitter input and control inputs except 3.3V TTL/
CMOS levels. They are not 5V tolerant.
3. The receiver powerdown feature when enabled wilI lock
receiver output to a logic low. However, the 5V/66 MHz
receiver maintain the outputs in the previous state when
powerdown occurred.
2.
DS90CR215 Pin Descriptions — Channel Link Transmitter
Pin Name
TxIN
TxOUT+
TxOUT−
TxCLK IN
TxCLK OUT+
TxCLK OUT−
PWR DWN
V
CC
GND
PLL V
CC
PLL GND
LVDS V
CC
LVDS GND
I/O
I
O
O
I
O
O
I
I
I
I
I
I
I
No.
21
3
3
1
1
1
1
4
5
1
2
1
3
TTL level input.
Positive LVDS differential data output.
Negative LVDS differential data output.
TTL level clock input. The rising edge acts as data strobe. Pin name TxCLK IN.
Positive LVDS differential clock output.
Negative LVDS differential clock output.
TTL level input. Assertion (low input) TRI-STATEs the outputs, ensuring low current at power
down.
Power supply pins for TTL inputs.
Ground pins for TTL inputs.
Power supply pins for PLL.
Ground pins for PLL.
Power supply pin for LVDS outputs.
Ground pins for LVDS outputs.
DS90CR216 Pin Descriptions — Channel Link Receiver
Pin Name
RxIN+
RxIN−
RxOUT
RxCLK IN+
RxCLK IN−
I/O
I
I
O
I
I
No.
3
3
21
1
1
Positive LVDS differential data inputs.
Negative LVDS differential data inputs.
TTL level data outputs.
Positive LVDS differential clock input.
Negative LVDS differential clock input.
Description
Description
13
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