DS90CP22
AC Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified (Note 4)
Symbol
T
SET
T
HOLD
T
SWITCH
T
PHZ
T
PLZ
T
PZH
T
PZL
T
LHT
T
HLT
T
JIT
Parameter
Input to SEL Setup Time,
Figures 1, 2
(Note 5)
Input to SEL Hold Time,
Figures 1, 2
(Note 5)
SEL to Switched Output,
Figures 1, 2
Disable Time (Active to TRI-STATE) High to Z,
Disable Time (Active to TRI-STATE) Low to Z,
Enable Time (TRI-STATE to Active) Z to High,
Enable Time (TRI-STATE to Active) Z to Low,
Output Low-to-High Transition Time, 20% to 80%,
Output High-to-Low Transition Time, 80% to 20%,
LVDS Data Path Peak to Peak Jitter, (Note
V
ID
= 300mV; 50% Duty Cycle; V
CM
=
1.2V at 800Mbps
V
ID
= 300mV; PRBS=2
23
-1 data
pattern; V
CM
= 1.2V at 800Mbps
T
PLHD
T
PHLD
T
SKEW
T
CCS
Propagation Low to High Delay,
Propagation Low to High Delay,
Propagation High to Low Delay,
Propagation High to Low Delay,
Pulse Skew |T
PLHD
- T
PHLD
|
Output Channel-to-Channel Skew,
V
CC
= 3.3V, T
A
= 25°C
V
CC
= 3.3V, T
A
= 25°C
0.9
1.0
0.9
1.0
290
290
Conditions
Min
0.7
1.0
0.9
Typ
0.5
0.5
1.2
2.1
3.0
25.5
25.5
400
400
40
65
1.3
1.3
1.3
1.3
0
35
1.7
4.0
4.5
55.0
55.0
580
580
90
120
1.6
1.5
1.6
1.5
225
80
Max
Units
ns
ns
ns
ns
ns
ns
ns
ps
ps
ps
ps
ns
ns
ns
ns
ps
ps
Note 4:
The parameters are guaranteed by design. The limits are based on statistical analysis of the device performance over PVT (process, voltage and
temperature) range.
Note 5:
T
SET
and T
HOLD
time specify that data must be in a stable state before and after the SEL transition.
Note 6:
The parameters are guaranteed by design. The limits are based on statistical analysis of the device performance over PVT range with the following
equipment test setup: HP70004A (display mainframe) with HP70841B (pattern generator), 5 feet of RG-142 cable with DUT test board and HP83480A (digital
scope mainframe) with HP83483A (20GHz scope module).
3
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