DS90C385/DS90C365
Transmitter Switching Characteristics
Symbol
TPPos0
TPPos1
TPPos2
TPPos3
TPPos4
TPPos5
TPPos6
TSTC
THTC
TCCD
Parameter
(Continued)
Over recommended operating supply and temperature ranges unless otherwise specified
Min
f = 85 MHz
−0.20
1.48
3.16
4.84
6.52
8.20
9.88
2.5
0
T
A
= 25˚C, V
CC
=
3.3V
f = 85 MHz
f = 65 MHz
f = 40 MHz
3.8
2.8
110
210
350
6.3
7.1
150
230
370
10
100
Typ
0
1.68
3.36
5.04
6.72
8.40
10.08
Max
0.20
1.88
3.56
5.24
6.92
8.60
10.28
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
ps
ps
ms
ns
Transmitter Output Pulse Position for Bit 0
(Figures 13, 14)
Transmitter Output Pulse Position for Bit 1
Transmitter Output Pulse Position for Bit 2
Transmitter Output Pulse Position for Bit 3
Transmitter Output Pulse Position for Bit 4
Transmitter Output Pulse Position for Bit 5
Transmitter Output Pulse Position for Bit 6
TxIN Setup to TxCLK IN
TxIN Hold to TxCLK IN
TxCLK IN to TxCLK OUT Delay
TxCLK IN to TxCLK OUT Delay
TJCC
Transmitter Jitter Cycle-to-Cycle
(Figures 15, 16)
TPLLS
TPDD
Transmitter Phase Lock Loop Set
Transmitter Power Down Delay
Note 5:
The Minimum and Maximum Limits are based on statistical analysis of the device performance over process, voltage, and temperature ranges. This
parameter is functionality tested only on Automatic Test Equipment (ATE).
Note 6:
The limits are based on bench characterization of the device’s jitter response over the power supply voltage range. Output clock jitter is measured with a
cycle-to-cycle jitter of +/−3ns applied to the input clock signal while data inputs are switching (See Figures 15 and 16). A jitter event of 3ns, represents worse case
jump in the clock edge from most graphics controller VGA chips currently available. This parameter is used when calculating system margin as described in AN-1059.
AC Timing Diagrams
10086804
FIGURE 1. “Worst Case” Test Pattern
www.national.com
4
NSC [ NATIONAL SEMICONDUCTOR ]
