Electrical Characteristics (Continued)
VCC = 3.3V unless otherwise indicated. Typicals and limits appearing in plain type apply for TA= TJ= 25˚C. Limits appearing in
boldface type apply over full Operating Temperature Range. Datasheet min/max specification limits are guaranteed by design,
test, or statistical analysis.
Symbol
GATE DRIVE
IQ-BOOT
Parameter
Conditions
Min
Typ
Max
Units
BOOT Pin Quiescent Current
High-Side MOSFET Driver
Pull-Up ON resistance
VBOOT = 12V, VSD = 0
18
90
µA
RHG_UP
@
VBOOT = 5V 350 mA Sourcing
2.7
Ω
RHG_DN
RLG_UP
High-Side MOSFET Driver
Pull-Down ON resistance
Low-Side MOSFET Driver Pull-Up
ON resistance
350 mA Sinking
0.8
2.7
0.8
Ω
Ω
Ω
@
VBOOT = 5V 350 mA Sourcing
RLG_DN
Low-Side MOSFET Driver
Pull-Down ON resistance
350 mA Sinking
OSCILLATOR
RFADJ = 750 kΩ
RFADJ = 100 kΩ
RFADJ = 42.2 kΩ
RFADJ = 18.7 kΩ
50
300
600
1000
PWM Frequency
475
725
fSW
kHz
External Synchronizing Signal
Frequency
Voltage Swing = 0V to VCC
fSW = 250 kHz to 1 MHz
fSW = 250 kHz to 1 MHz
250
1000
1
Synchronization Signal Low
Threshold
SYNCL
V
V
Synchronization Signal High
Threshold
SYNCH
DMAX
2
Max High-Side Duty Cycle
fSW = 300 kHz
fSW = 600 kHz
fSW = 1 MHz
86
78
67
%
LOGIC INPUTS AND OUTPUTS
VSTBY-IH Standby High Trip Point
VFB = 0.575V, VBOOT = 3.3V
VSD Rising
1.1
1.3
V
V
VSTBY-IL
Standby Low Trip Point
VFB = 0.575V, VBOOT = 3.3V
VSD Falling
0.232
VSD-IH
VSD-IL
SD Pin Logic High Trip Point
SD Pin Logic Low Trip Point
VSD Rising
V
V
V
V
VSD Falling
0.8
VPWGD-TH-LO PWGD Pin Trip Points
VPWGD-TH-HI PWGD Pin Trip Points
VFB Falling
0.408
0.677
0.434
0.710
60
0.457
0.742
VFB Rising
VPWGD-HYS
PWGD Hysteresis
VFB Falling
mV
VFB Rising
90
Note 1: Absolute maximum ratings indicate limits beyond which damage to the device may occur. Operating ratings indicate conditions for which the device
operates correctly. Operating Ratings do not imply guaranteed performance limits.
Note 2: The power MOSFETs can run on a separate 1V to 14V rail (Input voltage, V ). Practical lower limit of V depends on selection of the external MOSFET.
IN
IN
See the MOSFET GATE DRIVERS section under Application Information for further details.
Note 3: ESD using the human body model which is a 100pF capacitor discharged through a 1.5 kΩ resistor into each pin.
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