switching cycle. Figure 2 shows the SW node, HG, and LG
signals during pre-bias startup. The pre-biased output volt-
age should not exceed VCC + VGS of the external High-Side
MOSFET to ensure that the High-Side MOSFET will be able
to switch during startup.
Application Information (Continued)
is approximated by the curve FREQUENCY vs. FRE-
QUENCY ADJUST RESISTOR in the Typical Performance
Characteristics section.
When it is desired to synchronize the switching frequency
with an external clock source, the LM2747 has the unique
ability to synchronize from this external source within the
range of 250 kHz to 1 MHz. The external clock signal should
be AC coupled to the FREQ/SYNC pin as shown below in
Figure 1, where the RFADJ is chosen so that the fixed fre-
quency is approximately within 30% of the external syn-
chronizing clock frequency. An internal protection diode
clamps the low level of the synchronizing signal to approxi-
mately -0.5V. The internal clock synchrinizes to the rising
edge of the external clock.
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20150991
FIGURE 1. AC Coupled Clock
FIGURE 2. Output Pre-Bias Mode Waveforms
It is recommended to choose an AC coupling capacitance in
the range of 50 pF to 100 pF. Exceeding the recommended
capacitance may inject excessive energy through the inter-
nal clamping diode structure present on the FREQ/SYNC
pin.
TRACKING A VOLTAGE LEVEL
The LM2747 can track the output of a master power supply
during soft-start by connecting a resistor divider to the SS/
TRACK pin. In this way, the output voltage slew rate of the
LM2747 will be controlled by the master supply for loads that
require precise sequencing. When the tracking function is
used no soft-start capacitor should be connected to the
SS/TRACK pin. However in all other cases, a CSS value of at
least 1 nF between the soft-start pin and ground should be
used.
The typical trip level of the synchronization pin is 1.5V. To
ensure proper synchronization and to avoid damaging the
IC, the peak-to-peak value (amplitude) should be between
2.5V and VCC. The minimum width of this pulse must be
greater than 100 ns, and it’s maximum width must be 100ns
less than the period of the switching cycle.
The external clock synchronization process begins once the
LM2747 is enabled and an external clock signal is detected.
During the external clock synchronization process the inter-
nal clock initially switches at approximately 1.5 MHz and
decreases until it has matched the external clock’s fre-
quency. The lock-in period is approximately 30 µs if the
external clock is switching at 1 MHz, and about 100 µs if the
external clock is at 200 kHz. When there is no clock signal
present, the LM2747 enters into fixed-frequency mode and
begins switching at the frequency set by the RFADJ resistor.
If the external clock signal is removed after frequency syn-
chronization, the LM2747 will enter fixed-frequency mode
within two clock cycles. If the external clock is removed
within the 30 µs lock-in period, the LM2747 will re-enter
fixed-frequency mode within two internal clock cycles after
the lock-in period.
OUTPUT PRE-BIAS STARTUP
If there is a pre-biased load on the output of the LM2747
during startup, the IC will disable switching of the low-side
MOSFET and monitor the SW node voltage during the off-
time of the high-side MOSFET. There is no load current
sensing while in pre-bias mode because the low-side MOS-
FET never turns on. The IC will remain in this pre-bias mode
until it sees the SW node stays below 0V during the entire
high-side MOSFET’s off-time. Once it is determined that the
SW node remained below 0V during the high-side off-time,
the low-side MOSFET begins switching during the next
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FIGURE 3. Tracking Circuit
One way to use the tracking feature is to design the tracking
resistor divider so that the master supply’s output voltage
(VOUT1) and the LM2747’s output voltage (represented sym-
bolically in Figure 3 as VOUT2, i.e. without explicitly showing
the power components) both rise together and reach their
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