14.0 Instruction Set (Continued)
Registers
C
1 Bit of PSW Register for Carry
1 Bit of PSW Register for Half Carry
14.4.9 No-Operation Instruction
HC
GIE
The no-operation instruction does nothing, except to occupy
space in the program memory and time in execution.
1 Bit of PSW Register for Global Interrupt
Enable
No-Operation (NOP)
Note: The VIS is a special case of the Indirect Transfer of Control addressing
mode, where the double byte vector associated with the interrupt is
transferred from adjacent addresses in the program memory into the
program counter (PC) in order to jump to the associated interrupt ser-
vice routine.
VU
VL
Interrupt Vector Upper Byte
Interrupt Vector Lower Byte
Symbols
[B]
Memory Indirectly Addressed by B Register
Memory Indirectly Addressed by X Register
Direct Addressed Memory
14.5 REGISTER AND SYMBOL DEFINITION
[X]
The following abbreviations represent the nomenclature
used in the instruction description and the COP8
cross-assembler.
MD
Mem
Meml
Direct Addressed Memory or [B]
Direct Addressed Memory or [B] or
Immediate Data
Registers
A
8-Bit Accumulator Register
8-Bit Address Register
8-Bit Address Register
8-Bit Stack Pointer Register
15-Bit Program Counter Register
Upper 7 Bits of PC
Imm
Reg
8-Bit Immediate Data
B
Register Memory: Addresses F0 to FF
(Includes B, X and SP)
X
SP
PC
PU
PL
Bit
←
↔
Bit Number (0 to 7)
Loaded with
Exchanged with
Lower 8 Bits of PC
14.6 INSTRUCTION SET SUMMARY
←
←
ADD
ADC
A,Meml
A,Meml
ADD
A
A
A + Meml
A + Meml + C, C Carry,
←
ADD with Carry
←
HC Half Carry
← ←
A − MemI + C, C Carry,
SUBC
A,Meml
Subtract with Carry
A
←
HC Half Carry
←
AND
ANDSZ
OR
A,Meml
A,Imm
A,Meml
A,Meml
MD,Imm
A,Meml
A,Meml
A,Meml
#
Logical AND
A
A and Meml
=
Logical AND Immed., Skip if Zero
Logical OR
Skip next if (A and Imm)
0
←
←
A
A
A or Meml
XOR
IFEQ
IFEQ
IFNE
IFGT
IFBNE
DRSZ
SBIT
RBIT
IFBIT
RPND
X
Logical EXclusive OR
IF EQual
A xor Meml
=
Compare MD and Imm, Do next if MD Imm
=
Compare A and Meml, Do next if A Meml
IF EQual
≠
Compare A and Meml, Do next if A Meml
IF Not Equal
>
Compare A and Meml, Do next if A Meml
≠
Do next if lower 4 bits of B Imm
IF Greater Than
If B Not Equal
←
=
0
Reg
Decrement Reg., Skip if Zero
Set BIT
Reg Reg − 1, Skip if Reg
=
#,Mem
#,Mem
#,Mem
1 to bit, Mem (bit 0 to 7 immediate)
Reset BIT
0 to bit, Mem
IF BIT
If bit #, A or Mem is true do next instruction
Reset Software Interrupt Pending Flag
Reset PeNDing Flag
EXchange A with Memory
EXchange A with Memory [X]
LoaD A with Memory
LoaD A with Memory [X]
LoaD B with Immed.
LoaD Memory Immed.
LoaD Register Memory Immed.
EXchange A with Memory [B]
EXchange A with Memory [X]
↔
↔
←
←
←
A,Mem
A,[X]
A
A
A
A
B
Mem
[X]
X
LD
A,Meml
A,[X]
Meml
[X]
LD
LD
B,Imm
Imm
←
Mem Imm
LD
Mem,Imm
Reg,Imm
←
Reg Imm
LD
↔
↔
←
±
±
±
±
X
A, [B
A, [X
]
]
A
A
[B], (B
[X], (X
B
X
1)
1)
←
X
47
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