Fifth time through loop, set ATRMP1 = 0
Sixth time through loop, set ATRMP0 = 0
28. Go to step 22.
15.0 A/D Converter (Continued)
9. Wait 1.05 ms for the amplifier to settle.
10. Load 01h into ENAD to perform an A/D Conversion.
11. Store the result registers.
29. Reset CALP bit = 0, but leave ATRMP6:0 unchanged.
30. Reset the TRIM bit to 0.
12. If the three most significant bits of the result are all ones
and ATRMN6 = 1, go to step 8.
15.3 A/D OPERATION
Else, if the three most significant bits are all zeros and
ATRMN6 = 1, go to step 13.
The A/D conversion is completed within fifteen A/D converter
clocks. The A/D Converter interface works as follows. Setting
the ADBSY bit in the A/D control register ENAD initiates an
A/D conversion. The conversion sequence starts at the be-
ginning of the write to ENAD operation which sets ADBSY,
thus powering up the A/D. At the first edge of the Converter
clock following the write operation, the sample signal turns
on for three clock cycles. At the end of the conversion, the
internal conversion complete signal will clear the ADBSY bit
and power down the A/D. The A/D 10-bit result is immedi-
ately loaded into the A/D result registers (ADRSTH and
ADRSTL) upon completion during TCSTART. This prevents
transient data (resulting from the A/D writing a new result
over an old one) being read from ADRSLT.
Else, if the three most significant bits are all ones and
ATRMN6 = 0, go to step 13.
Else, if the three most significant bits are all zeros and
ATRMN6 = 0, go to step 8.
Go to step 15.
13. First time through loop, set ATRMP5 = 0
Second time through loop, set ATRMP4 = 0
Third time through loop, set ATRMP3 = 0
Fourth time through loop, set ATRMP2 = 0
Fifth time through loop, set ATRMP1 = 0
Sixth time through loop, set ATRMP0 = 0
14. Go to step 8.
Inadvertent changes to the ENAD register during conversion
are prevented by the control logic of the A/D. Any attempt to
write any bit of the ENAD Register except ADBSY, while
ADBSY is a one, is ignored. ADBSY must be cleared either
by completion of an A/D conversion or by the user before the
prescaler, conversion mode or channel select values can be
changed. After stopping the current conversion, the user can
load different values for the prescaler, conversion mode or
channel select and start a new conversion in one instruction.
15. Reset CALN bit = 0, but leave ATRMN6 : 0 unchanged.
16. Load C0h into the AMPTRMP register to select VREFP
and the no-trim value.
17. Wait 1.05 ms for the amplifier to settle.
18. Load 01h into ENAD to perform an A/D Conversion.
19. Store the result registers.
20. If the three most significant bits of the result are all ones,
go to step 22.
15.3.1 Prescaler
The A/D Converter (A/D) contains a prescaler option that
allows two different clock selections. The A/D clock fre-
quency is equal to MCLK divided by the prescaler value.
Note that the prescaler value must be chosen such that the
A/D clock falls within the specified range. The maximum A/D
frequency is 1.67 MHz. This equates to a 600 ns A/D clock
cycle.
Else, if the three most significant bits are all zeros, go to
step 21.
Else, goto step 29.
21. Set ATRMN6 = 0
22. First time through loop, set ATRMN5=1
Second time through loop, set ATRMN4=1
Third time through loop, set ATRMN3=1
Fourth time through loop, set ATRMN2=1
Fifth time through loop, set ATRMN1=1
Sixth time through loop, set ATRMN0=1
Seventh time through loop, go to step 29.
23. Wait 1.05 ms for the amplifier to settle.
24. Load 01h into ENAD to perform an A/D Conversion.
25. Store the result registers.
The A/D Converter takes 15 A/D clock cycles to complete a
conversion. Thus the minimum A/D conversion time is 12 µs
when a prescaler of 16 has been selected with MCLK = 20
MHz. The 15 A/D clock cycles needed for conversion consist
of 3 cycles for sampling, 1 cycle for auto-zeroing the com-
parator, 10 cycles for converting, 1 cycle for loading the
result into the result registers and for stopping and re-
initializing. The ADBSY flag provides an A/D clock inhibit
function, which saves power by powering down the A/D
when it is not in use.
Note: The A/D Converter is also powered down when the device is in either
the HALT or IDLE modes. If the A/D is running when the device enters
the HALT or IDLE modes, the A/D powers down and then restarts the
conversion from the beginning with a corrupted sampled voltage (and
thus an invalid result) when the device comes out of the HALT or IDLE
modes.
26. If the three most significant bits of the result are all ones
and ATRMN6 = 1, go to step 22.
Else, if the three most significant bits are all zeros and
ATRMN6 = 1, go to step 27.
Else, if the three most significant bits are all ones and
ATRMN6 = 0, go to step 27.
Note: If a Breakpoint is issued during an A/D conversion, the conversion will
be completed.
Else, if the three most significant bits are all zeros and
ATRMN6 = 0, go to step 22.
15.4 ANALOG INPUT AND SOURCE RESISTANCE
CONSIDERATIONS
Go to step 29.
Figure 29 shows the A/D pin model in single ended mode.
The differential mode has a similar A/D pin model. The leads
to the analog inputs should be kept as short as possible.
Both noise and digital clock coupling to an A/D input can
cause conversion errors. The clock lead should be kept
away from the analog input line to reduce coupling.
27. First time through loop, set ATRMP5 = 0
Second time through loop, set ATRMP4 = 0
Third time through loop, set ATRMP3 = 0
Fourth time through loop, set ATRMP4 = 0
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