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COP8AME9EMW8 参数 Datasheet PDF下载

COP8AME9EMW8图片预览
型号: COP8AME9EMW8
PDF下载: 下载PDF文件 查看货源
内容描述: 8位CMOS闪存微控制器,具有8K内存,双通道运算放大器,虚拟EEROM ,温度传感器, 10位A / D和掉电复位 [8-Bit CMOS Flash Microcontroller with 8k Memory, Dual Op Amps, Virtual EEROM, Temperature Sensor,10-Bit A/D and Brownout Reset]
分类和应用: 闪存传感器温度传感器微控制器和处理器外围集成电路运算放大器光电二极管时钟
文件页数/大小: 83 页 / 908 K
品牌: NSC [ National Semiconductor ]
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necessary to adjust both pairs. This is done with the use of  
two volatile registers, AMPTRMN and AMPTRMP, and some  
on-chip circuits. The two trim registers will allow for trimming  
out the offset in 0.5 mV steps in either direction. Once the  
amplifier is trimmed, the trim values are stored in AMPTRMN  
and AMPTRMP. Retrimming is necessary after any type of  
Reset. These two registers are initialized to 040 (hex) on a  
Reset.  
15.0 A/D Converter (Continued)  
15.2.2 Programmable Gain Amplifier Offset Calibration  
The programmable gain amplifier has an offset that could be  
as high as  
7 mV. When using this amplifier, a user may  
want to nullify this offset to obtain more accurate measure-  
ments with the A/D converter. Since this amplifier has both  
an N channel and P channel pair on its input stage, it’s  
TABLE 31. AMPTRMN  
Bit 4 Bit 3  
ATRMN4 ATRMN3  
Bit 7  
Bit 6  
Bit 5  
Bit 2  
Bit 1  
Bit 0  
CALN  
ATRMN6  
ATRMN5  
ATRMN2  
ATRMN1  
ATRMN0  
CALN  
Enables the internal reference, VREFN, for  
trimming the N channel pair. Enabled = 1, Dis-  
abled = 0. This bit, when = 1, also disables the  
analog multiplexor. To perform the trimming al-  
gorithm, the TRIM bit must also = 1.  
signed magnitude method. ATRMN6 is the sign  
bit. When ATRMN6 = 1, it compensates for  
positive offset. When ATRMN6 = 0, it compen-  
sates for negative offset. ATRMN5:0 are the  
magnitude of the trim with 000000 = no trim  
value and 111111 = highest trim value.  
ATRMN6:0 Trim bits used for actual trimming. It uses a  
TABLE 32. AMPTRMP  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
CALP  
ATRMP6  
ATRMP5  
ATRMP4  
ATRMP3  
ATRMP2  
ATRMP1  
ATRMP0  
CALP  
Enables the internal reference, VREFP, for  
trimming the P channel pair. Enabled = 1,  
Disabled =0. This bit, when = 1, also disables  
the analog multiplexor. To perform the trim-  
ming algorithm, the TRIM bit must also = 1.  
The on-chip temperature sensor could also be used to mea-  
sure temperature variations and determine whether retrim-  
ming of the offset is necessary.  
ATRMNP6:0 Trim bits used for actual trimming. It uses a  
signed magnitude method. ATRMP6 is the  
sign bit. When ATRMP6 = 1, it compensates  
for positive offset. When ATRMP6 = 0, it com-  
pensates for negative offset. ATRMP5:0 are  
the magnitude of the trim with 000000 = no  
trim value and 111111 = highest trim value.  
20006358  
FIGURE 28. Offset Trim Configuration when TRIM = 1  
15.2.3 Trimming the Offset on the Programmable Gain  
Amplifier  
The procedure to trim both the N channel pair and P channel  
pair are listed below. Steps 1–14 trim the N channel pair and  
steps 15–30 trim the P channel pair.  
Setting the TRIM bit puts the programmable gain amplifier  
into a special configuration used for trimming the offset,  
which is shown in Figure 28. This configuration enables the  
amplifier and puts it into open loop gain. By selecting the  
reference voltages, VREFN and VREFP, one at a time, the  
offset can be calibrated using the A/D converter. The calibra-  
tion routine uses software to perform a successive approxi-  
mation algorithm and is indicated below. After the trim algo-  
rithm is complete, the trim values are stored in the  
AMPTRMN and AMPTRMP registers and should remain,  
unchanged, until the algorithm is executed again. The trim  
values stored in AMPTRMN and AMPTRMP values are lost  
if any type of reset is generated. Therefore, it’s necessary to  
retrim after any type of Reset. A method to minimize retrim-  
ming would be to store the initial trim values into the virtual  
EEPROM memory in addition to AMPTRMN and AMPTRMP.  
Then, whenever necessary, the trim values could be re-  
trieved from virtual EEPROM, avoiding execution of the trim  
algorithm upon a Reset.  
Note: AN-1199 contains sample assembly code which implements the  
trim algorithm outline on step 1-30.  
1. Set the TRIM bit = 1 in the ADGAIN register to configure  
the amplifier.  
2. Load C0h into the AMPTRMN register to select VREFN  
and the no-trim value.  
3. Wait 1.05 ms for the amplifier to settle.  
4. Load 01h into ENAD to perform an A/D Conversion.  
5. Store the result registers.  
6. If the three most significant bits of the result are all ones,  
go to step 8.  
Else, if the three most significant bits are all zeros, go to  
step 7.  
Else, goto step 15.  
7. Set ATRMN6 = 0  
8. First time through loop, set ATRMN5 = 1  
Second time through loop, set ATRMN4 = 1  
Third time through loop, set ATRMN3 = 1  
Fourth time through loop, set ATRMN2 = 1  
Fifth time through loop, set ATRMN1 = 1  
Sixth time through loop, set ATRMN0 = 1  
Seventh time through loop, go to step 15.  
The amplifier offset can drift slightly as the temperature  
changes. For example, over the entire temperature range of  
−40˚C to +125˚C, the drift could be typically 2 mV. If the user  
application is in a constantly changing temperature, and this  
offset drift is a problem, it is recommended that the amplifier  
be retrimmed periodically, or before critical measurements.  
53  
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