A
2-Tone, 3rd Order IMD Intercept
plot is found in the
Typical Performance Characteristics
section. The
output power level is taken at the load. Third-order
harmonic distortion is calculated with the formula:
HD3
rd
= 2
•
(IP3
o
– P
o
)
where:
The CLC449 noise model in Figure 8 is used to develop
the equation below.
The equation for Noise Figure (NF) is:
e
+
i R
2
+
4
k
TR
+
i
⋅
R ||R
2
+
4
k
T
⋅
R ||R
2
(
bn s
)
g
s
g
bi
f
f
NF
=
10LOG
ni
4
k
TR
s
(
)
•
IP3
o
= third-order output intercept, dBm at
the load.
•
P
o
= output power level, dBm at the load.
•
HD3
rd
= third-order distortion from the
fundamental, -dBc.
•
dBm is the power in mW, at the load,
expressed in dB.
Realized third-order output distortion is highly
dependent upon the external circuit. Some of the
common external circuit choices that improve 3
rd
order
distortion are:
where:
•
R
s
is the source resistance at the non-
•
•
inverting input.
There is no matching resistor from the input
to ground.
e
ni
, i
bn
, i
bi
are the voltage and current noise
density terms (see in the
Distortion and
Noise Response
sub-section of the
Electrical
Characteristics
section).
4kT = 16 x 10
-21
J, T = 290°K.
R
f
is the feedback resistor and R
g
is the gain
setting resistor.
•
•
•
short and equal return paths from the load
to the supplies.
•
de-coupling capacitors of the correct value.
•
higher load resistance.
•
a lower ratio of the output swing to the power
supply voltage.
Dynamic Range (Noise)
In RF applications, noise is frequently specified as Noise
Figure (NF). Figure 7 plots NF for the CLC449 at a gain
of 10, with a feedback resistor R
f
of 100Ω, and with no
input matching resistor. The minimum Noise Figure
(2.5dB) for these conditions occurs when the source
resistance equals 700Ω.
20
Printed Circuit Board Layout and Measurement
High Frequency op amp performance is strongly depen-
dent on proper layout, proper resistive termination and
adequate power supply decoupling. The most important
layout points to follow are:
•
Use a ground plane.
•
Bypass power supply pins with monolithic
•
•
•
•
capacitors of about 0.1µF value and place
the capacitors less than 0.1” (3mm) from the pin.
Bypass power supply pins with 6.8µF tantalum
capacitors for large signal current swings or
improved power supply noise rejection.
Minimize trace and lead lengths for components
between the inverting and output pins.
Remove ground plane underneath the
amplifier package and within 0.1” (3mm) of all
input/output pads.
If parts must be socketed, always use
flush-mount socket pins instead of high profile
sockets.
Noise Figure (dB)
15
10
5
0
10
100
1000
10000
Source Resistance (Ω)
Evaluation boards are available for proto-typing and mea-
surements.
Additional
layout
information
is
available in the evaluation board literature.
Figure 7. Noise Figure Plot
R
s
V
s
+
-
e
n
*
*
i
bn
+
CLC449
-
V
o
R
f
*
i
bi
R
g
Figure 8: CLC449 Noise Model
7
http://www.national.com
NSC [ NATIONAL SEMICONDUCTOR ]
