AC Electrical Characteristics
(Continued)
The following specifications apply for V
CC
= 5V, t
r
= t
f
= 20 ns, V
REF
(+) = 5V, V
REF
(−) = 0V and T
A
= 25˚C unless otherwise speci-
fied.
Typ
Parameter
t
ACC2
, Access Time (Delay from
Falling Edge of RD to Output
Valid)
t
ACC3
, Access Time (Delay from
Rising Edge of RDY to Output
Valid)
t
I
, Internal Comparison Time
t
1H
, t
0H
, TRI-STATE Control
(Delay from Rising Edge of RD to
Hi-Z State)
t
INTL
, Delay from Rising Edge of
WR to Falling Edge of INT
t
INTH
, Delay from Rising Edge of
RD to Rising Edge of INT
t
INTHWR
, Delay from Rising Edge of
WR to Rising Edge of INT
t
RDY
, Delay from CS to RDY
t
ID
, Delay from INT to Output Valid
t
RI
, Delay from RD to INT
t
P
, Delay from End of Conversion
to Next Conversion
Slew Rate, Tracking
C
VIN
, Analog Input Capacitance
C
OUT
, Logic Output Capacitance
C
IN
, Logic Input Capacitance
Pin 7 = V
CC
, C
L
= 50 pF
t
RD
>
t
I
;
Figure 4
t
RD
<
t
I
;
Figure 3
t
RD
+200
125
175
50
20
200
t
I
t
RD
+290
225
270
100
50
290
500
0.1
45
5
5
ns
ns
ns
ns
ns
ns
ns
ns
V/µs
pF
pF
pF
Conditions
Pin 7 = V
CC
, t
RD
>
t
I
;
Figure 4
C
L
= 15 pF
C
L
= 100 pF
R
PULLUP
= 1k and C
L
= 15 pF
(Note 6)
Tested
Limit
(Note 7)
70
90
30
Design
Limit
(Note 8)
120
150
ns
ns
ns
Units
Pin 7 = V
CC
;
Figures 4, 5
C
L
= 50 pF
R
L
= 1k, C
L
= 10 pF
800
100
1300
200
ns
ns
Figures 2, 3, 4
C
L
= 50 pFc
Figure 5,
C
L
= 50 pF
Figure 2,
C
L
= 50 pF, Pin 7 = 0
Figure 5
Pin 7 = V
CC
, t
RD
<
t
I
Figure 3
Figures 2, 3, 4, 5
(Note 4) See Graph
Note 1:
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions.
Note 2:
All voltages are measured with respect to the GND pin, unless otherwise specified.
Note 3:
Total unadjusted error includes offset, full-scale, and linearity errors.
Note 4:
Accuracy may degrade if t
WR
or t
RD
is shorter than the minimum value specified. See Accuracy vs t
WR
and Accuracy vs t
RD
graphs.
Note 5:
When the input voltage (V
IN
) at any pin exceeds the power supply rails (V
IN
<
V
−
or V
IN
>
V
+
) the absolute value of current at that pin should be limited to
1 mA or less. The 4 mA package input current limits the number of pins that can exceed the power supply boundaries with a 1 mA current limit to four.
Note 6:
Typicals are at 25˚C and represent most likely parametric norm.
Note 7:
Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 8:
Design limits are guaranteed but not 100% tested. These limits are not used to calculate outgoing quality levels.
Note 9:
Human body model, 100 pF discharaged through a 1.5 kΩ resistor.
5
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