Description of Pin Functions
Pin
1
2
3
4
5
6
Name
V
IN
DB0
DB1
DB2
DB3
WR
/RDY
Function
Analog input; range = GND≤V
IN
≤V
CC
TRI-STATE data output — bit 0 (LSB)
TRI-STATE data output — bit 1
TRI-STATE data output — bit 2
TRI-STATE data output — bit 3
WR-RD Mode
WR:
With CS low, the conversion is
started on the falling edge of WR.
Approximately 800 ns (the preset internal
time out, t
I
) after the WR rising edge, the
result of the conversion will be strobed
into the output latch, provided that RD
does not occur prior to this time out (see
Figures 3, 4
).
RD Mode
RDY:
This is an open drain output (no
internal pull-up device). RDY will go low
after the falling edge of CS; RDY will go
TRI-STATE when the result of the
conversion is strobed into the output
latch. It is used to simplify the interface
to a microprocessor system (see
Figure
2
).
7
Mode
Mode:
Mode selection input — it is
internally tied to GND through a 50 µA
current source.
RD Mode:
When mode is low
WR-RD Mode:
When mode is high
8
RD
WR-RD Mode
With CS low, the TRI-STATE data
outputs (DB0-DB7) will be activated
when RD goes low (see
Figure 5
). RD
can also be used to increase the speed
of the converter by reading data prior to
the preset internal time out (t
I
,
z
800 ns).
If this is done, the data result transferred
to output latch is latched after the falling
edge of the RD (see
Figures 3, 4
).
RD Mode
With CS low, the conversion will start
with RD going low, also RD will enable
the TRI-STATE data outputs at the
completion of the conversion. RDY going
TRI-STATE and INT going low indicates
the completion of the conversion (see
Figure 2
).
Pin
9
Name
INT
WR-RD Mode
Function
INT going low indicates that the
conversion is completed and the data
result is in the output latch. INT will go
low,
z
800 ns (the preset internal time
out, t
I
) after the rising edge of WR (see
Figure 4
); or INT will go low after the
falling edge of RD , if RD goes low prior
to the 800 ns time out (see
Figure 3).
INT is reset by the rising edge of RD or
CS (see
Figures 3, 4
).
RD Mode
INT going low indicates that the
conversion is completed and the data
result is in the output latch. INT is reset
by the rising edge of RD or CS (see
Figure 2
).
10
11
12
13
14
15
16
17
18
GND
V
REF
(−)
V
REF
(+)
CS
DB4
DB5
DB6
DB7
OFL
Ground
The bottom of resistor ladder, voltage
range: GND≤V
REF
(−)≤V
REF
(+) (Note 5)
The top of resistor ladder, voltage range:
V
REF
(−)≤V
REF
(+)≤V
CC
(Note 5)
CS must be low in order for the RD or
WR to be recognized by the converter.
TRI-STATE data output — bit 4
TRI-STATE data output — bit 5
TRI-STATE data output — bit 6
TRI-STATE data output — bit 7 (MSB)
Overflow output — If the analog input is
higher than the V
REF
(+), OFL will be low
at the end of conversion. It can be used
to cascade 2 or more devices to have
more resolution (9, 10-bit). This output is
always active and does not go into
TRI-STATE as DB0–DB7 do.
No connection
Power supply voltage
19
20
NC
V
CC
1.0 Functional Description
1.1 GENERAL OPERATION
The ADC0820 uses two 4-bit flash A/D converters to make
an 8-bit measurement (Figure
1
). Each flash ADC is made
up of 15 comparators which compare the unknown input to a
reference ladder to get a 4-bit result. To take a full 8-bit read-
ing, one flash conversion is done to provide the 4 most sig-
nificant data bits (via the MS flash ADC). Driven by the 4
9
MSBs, an internal DAC recreates an analog approximation
of the input voltage. This analog signal is then subtracted
from the input, and the difference voltage is converted by a
second 4-bit flash ADC (the LS ADC), providing the 4 least
significant bits of the output data word.
The internal DAC is actually a subsection of the MS flash
converter. This is accomplished by using the same resistor
www.national.com
NSC [ NATIONAL SEMICONDUCTOR ]
