DC Electrical Characteristics
The following specifications apply for V
CC
= 5V, unless otherwise specified.
Boldface limits apply from T
MIN
to T
MAX
; all other
limits T
A
= T
J
= 25˚C.
Parameter
Conditions
ADC0820CCJ
Typ
(Note 6)
V
IN(1)
, Logical “1”
Input Voltage
V
IN(0)
, Logical “0”
Input Voltage
I
IN(1)
, Logical “1”
Input Current
I
IN(0)
, Logical “0”
Input Current
V
OUT(1)
, Logical “1”
Output Voltage
V
IN(1)
= 5V; WR
V
IN(1)
= 5V; Mode
V
IN(0)
= 0V; CS , RD , WR ,
Mode
V
CC
= 4.75V, I
OUT
= −360 µA;
DB0–DB7, OFL , INT
V
CC
= 4.75V, I
OUT
= −10 µA;
DB0–DB7, OFL , INT
V
OUT(0)
, Logical “0”
Output Voltage
I
OUT
, TRI-STATE
Output Current
I
SOURCE
, Output
Source Current
I
SINK
, Output Sink
Current
I
CC
, Supply Current
V
CC
= 4.75V, I
OUT
= 1.6 mA;
DB0–DB7, OFL , INT , RDY
V
OUT
= 5V; DB0–DB7, RDY
V
OUT
= 0V; DB0–DB7, RDY
V
OUT
= 0V; DB0–DB7, OFL
INT
V
OUT
= 5V; DB0–DB7, OFL ,
INT , RDY
CS = WR = RD = 0
7.5
15
7.5
13
15
mA
0.1
−0.1
−12
−9
14
3
−3
−6
−4.0
7
0.1
−0.1
−12
−9
14
0.3
−0.3
−7.2
−5.3
8.4
3
−3
−6
−4.0
7
µA
µA
mA
mA
mA
0.4
0.34
0.4
V
4.5
4.6
4.5
V
2.4
2.8
2.4
V
V
CC
= 4.75V
V
CC
= 5.25V
CS , WR , RD
Mode
CS , WR , RD
Mode
V
IN(1)
= 5V; CS , RD
0.005
0.1
50
−0.005
Tested
Limit
(Note 7)
2.0
3.5
0.8
1.5
1
3
200
−1
0.005
0.1
50
−0.005
0.3
170
Design
Limit
(Note 8)
ADC0820BCN, ADC0820CCN
ADC0820BCV, ADC0820BCWM
ADC0820CCWM, ADC0820CIWM
Typ
(Note 6)
Tested
Limit
(Note 7)
2.0
3.5
0.8
1.5
Design
Limit
(Note 8)
2.0
3.5
0.8
1.5
1
3
200
−1
V
V
V
V
µA
µA
µA
µA
Limit
Units
AC Electrical Characteristics
The following specifications apply for V
CC
= 5V, t
r
= t
f
= 20 ns, V
REF
(+) = 5V, V
REF
(−) = 0V and T
A
= 25˚C unless otherwise speci-
fied.
Typ
Parameter
t
CRD
, Conversion Time for RD
Mode
t
ACC0
, Access Time (Delay from
Falling Edge of RD to Output
Valid)
t
CWR-RD
, Conversion Time for
WR-RD Mode
t
WR
, Write Time
t
RD
, Read Time
Min
Max
Min
Pin 7 = V
CC
; t
WR
= 600 ns,
t
RD
= 600 ns;
Figures 3, 4
Pin 7 = V
CC
;
Figures 3, 4
(Note 4) See Graph
Pin 7 = V
CC
;
Figures 3, 4
(Note 4) See Graph
Pin 7 = V
CC
, t
RD
<
t
I
;
Figure 3
C
L
= 15 pF
C
L
= 100 pF
50
600
600
1.52
µs
ns
µs
ns
Conditions
Pin 7 = 0,
Figure 2
Pin 7 = 0,
Figure 2
(Note 6)
1.6
t
CRD
+20
Tested
Limit
(Note 7)
Design
Limit
(Note 8)
2.5
t
CRD
+50
µs
ns
Units
t
ACC1
, Access Time (Delay from
Falling Edge of RD to Output
Valid)
190
210
280
320
ns
ns
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