Integrated Functions (Continued)
4.6.1.4 Video Refresh
make up a character row; within that row, the ATTR must
fetch successive scan lines from the glyph table so as to
draw proper characters. Graphics modes are somewhat
simpler. In CGA-compatible mode, a DWORD provides
eight pixels. The first four pixels come from planes 0 and
2; each 4-bit pixel gets bits [3:2] from plane 2, and bits
[1:0] from plane 0. The remaining four pixels come from
planes 1 and 3. The EGA-compatible mode also gets
eight pixels from a DWORD, but each pixel gets one bit
from each plane, with plane 3 providing bit 3. Finally,
VGA-compatible mode gets four pixels from each
DWORD; plane 0 provides the first pixel, plane 1 the next,
and so on. The 8 bpp mode uses an option to provide
every pixel for two dot clocks, thus allowing the refresh
pipe to keep up (it only increments on character clocks)
and meaning that the 320-pixel-wide mode 13h really has
640 visible pixels per line. The VGA color model is
unusual. The ATTR contains a 16-entry color palette with
6 bits per entry. Except for 8 bpp modes, all VGA configu-
rations drive four bits of pixel data into the palette, which
produces a 6-bit result. Based on various control regis-
ters, this value is then combined with other register con-
tents to produce an 8-bit index into the DAC. There is a
ColorPlaneEnable register to mask bits out of the pixel
data before it goes to the palette; this is used to emulate
four-color CGA modes by ignoring the top two bits of each
pixel. In 8 bpp modes, the palette is bypassed and the
pixel data goes directly to the DAC.
VGA refresh is controlled by two units: the CRT controller
(CRTC) and the attribute controller (ATTR). The CRTC
provides refresh addresses and video control; the ATTR
provides the refresh datapath, including pixel formatting
and internal palette lookup.
The VGA back end contains two basic clocks: the dot
clock (or pixel clock) and the character clock. The Clock-
Select field of the Miscellaneous Output register selects a
“master clock” of either 25 MHz or 28 MHz. This master
clock, optionally divided by two, drives the dot clock. The
character clock is simply the dot clock divided by eight or
nine.
The VGA supports four basic pixel formats. Using text for-
mat, the VGA interprets frame buffer values as ASCII
characters, foreground/background attributes, and font
data. The other three formats are all “graphics modes”,
known as APA (All Points Addressable) modes. These for-
mats could be called CGA-compatible (odd/even 4-bpp),
EGA-compatible (4-plane 4-bpp), and VGA-compatible
(pixel-per-byte 8-bpp). The format is chosen by the
ShiftRegister field of the Graphics Controller Mode regis-
ter.
The refresh address pipe is an integral part of the CRTC,
and has many configuration options. Refresh can begin at
any frame buffer address. The display width and the frame
buffer pitch (scan-line delta) are set separately. Multiple
scan lines can be refreshed from the same frame buffer
addresses. The LineCompare register causes the refresh
address to be reset to zero at a particular scan line, pro-
viding support for vertical split-screen.
4.6.1.5 VGA Video BIOS
The video BIOS supports the VESA BIOS Extensions
(VBE) Version 1.2 and 2.0, as well as all standard VGA
BIOS calls. It interacts with Virtual VGA through the use of
several extended VGA registers. These are virtual regis-
ters contained in the VSA code for Virtual VGA. (These
registers are defined in a separate document.)
Within the context of a single scan line, the refresh
address increments by one on every character clock.
Before being presented to the frame buffer, refresh
addresses can be shifted by 0, 1, or 2 bits to the left.
These options are often mis-named BYTE, WORD, and
DWORD modes. Using this shifter, the refresh unit can be
programmed to skip one out of two or three out of four
DWORDs of refresh data. As an example of the utility of
this function, consider Chain 4 mode, described in Section
4.6.1.3 “Address Mapping” on page 158. Pixels written in
Chain 4 mode occupy one out of every four DWORDs in
the frame buffer. If the refresh path is put into “Double-
word” mode, the refresh will come only from those
DWORDs writable in Chain 4. This is how VGA mode 13h
works.
4.6.2 Virtual VGA
The GXLV processor reduces the burden of legacy hard-
ware by using a balanced mix of hardware and software to
provide the same functionality. The graphics pipeline con-
tains full hardware support for the VGA “front-end”, the
logic that controls read and write operations to the VGA
frame buffer (located in graphics memory). For some
modes, the hardware can also provide direct display of the
data in the VGA buffer. Virtual VGA traps frame buffer
accesses only when necessary, but it must trap all VGA
I/O accesses to maintain the VGA state and properly pro-
gram the graphics pipeline and display controller.
In text mode, the ATTR has a lot of work to do. At each
character clock, it pulls a DWORD of data out of the frame
buffer. In that DWORD, plane 0 contains the ASCII char-
acter code, and plane 1 contains an attribute byte. The
ATTR uses plane 0 to generate a font lookup address and
read another DWORD. In plane 2, this DWORD contains a
bit-per-pixel representation of one scan line in the appro-
priate character glyph. The ATTR transforms these bits
into eight pixels, obtaining foreground and background
colors from the attribute byte. The CRTC must refresh
from the same memory addresses for all scan lines that
The processor core contains SMI generation hardware for
VGA memory write operations. The bus controller con-
tains SMI generation hardware for VGA I/O read and write
operations. The graphics pipeline contains hardware to
detect and process reads and writes to VGA memory.
VGA memory is partitioned from system memory.
VGA functionality with the GXLV processor includes the
standard VGA modes (VGA, EGA, CGA, and MDA) as
well as the higher-resolution VESA modes. The CGA and
MDA modes (modes 0 through 7) require that Virtual VGA
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