Integrated Functions (Continued)
4.5.14.1 CS5530 Video Port Data Transfer
VID_DATA[7:0] is advanced when both VID_VAL and
VID_RDY are asserted. VID_RDY is driven one clock
early to the GXLV processor while VID_VAL is driven coin-
cident with VID_DATA[7:0]. A sample interface functional
timing diagram is shown in Figure 4-17.
VID_VAL indicates that the GXLV processor has placed
valid data on VID_DATA[7:0]. VID_RDY indicates that the
CS5530 is ready to accept the next byte of video data.
VID_CLK
8 + 3 CLKs
VID_VAL
VID_RDY
8 CLKs
3 CLKs
VID_DATA
[7:0]
4 CLKs
8 CLKs
1
2
1
2
2
4 CLKs
Invalid Data
CLK CLKs CLK CLKs
CLKs
Note: VID_CLK = CORE_CLK/2
Figure 4-17. Video Port Data Transfer (CS5530)
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