Index (Continued)
BC_DRAM_TOP (8000h-8003h)
BC_XMAP_1 (8004h-8007h)
BC_XMAP_2 (8008h-800Bh)
BC_XMAP_3 (800Ch-800Fh)
Internal Test Signals
Ifloat
101
101
101
101
SDRAM Interface Clocking
CAS latency
SDRAM Read Cycle
SDRAM Refresh Cycle
SDRAM Write Cycle
SHFTSDCLK
118
118
115
117
116
119
103
32
32
32
33
32
32
32
33
33
Raw Clock
SDRAM Test Outputs
Test
Test Clock
Test Data Input
X-Bus
Memory Controller Interface Signals
Bank Address Bits
29
29
30
29
30
29
29
30
29
108
108
108
108
108
108
108
108
29
Chip Selects
Clock Enable
Test Data Output
Thermal Diode Negative (TDN)
Thermal Diode Positive (TDP)
Interrupt
Interrupt and Exception Priorities
Interrupt Descriptor Table
Interrupt Request Level 13
Interrupts
Column Address Strobe
Data Mask Control Bits
Memory Address Bus
Row Address Strobe
SDRAM Clocks
76
75
25
74
74
74
77
77
Write Enable
Memory Controller Register
MC_BANK_CFG (8408h-840Bh)
MC_DR_ACC (841Ch-841Fh)
MC_DR_ADD (8418h-841Bh)
MC_GBASE_ADD (8414h-8417h)
MC_MEM_CNTRL1 (8400h-8403h)
MC_MEM_CNTRL2 (8404h-8407h)
MC_SYNC_TIM1 (840Ch-840Fh)
Memory Data Bus
MMX Instruction Set
Multiplexed Address
PCI pins
Multiplexed Command
Configuration Read
INTR
NMI
Real Mode Error Codes
Real Mode, Exceptions
SMM
74
75
Vector A
INTR
invalid opcode
IRET instruction
43, 74, 76, 83, 85, 86
39
43
229
26
L
Legacy VGA
165
66
28
39
112
26
26
26
26
26
26
26
Local Descriptor Table Register (LDTR)
LOCK
Lock Prefix
Configuration Write
Dual Address Cycle
Memory Read Line
Memory Read Multiple
Memory Write and Invalidate
Special Cycle
Low Order Interleaving
M
MediaGX™ Virtual VGA
Memory Address Space
Memory Addressing
Paging Mechanism
Memory Addressing Modes
Memory Controller
Auto LOI
167
60
Multiplexed Command and Byte Enables
Interrupt Acknowledge
Multitasking
26
70
72
61
N
NMI
103–119
49, 74, 75, 76, 78, 83, 85, 86
112
notebook computers
174
1 DIMM Bank
113
O
2 DIMM Banks
Block Diagram
113
103
Overflow Flag
43
DRAM Address Conversion
DRAM Configuration
Graphics Pipeline
Memory Array Configuration
Memory Cycles
Memory Organization
Non-Auto LOI
1 DIMM Bank
2 DIMM Banks
Page Miss
Processor Interface
SDRAM
112
105
103
104
115
105
P
Package Outlines
Package Specifications
Page Table Entry
palette lookup
198
195
73
166
164
PCI Arbitration
PCI Configuration Registers
Access Format
114
114
117
103
104
106
107
106
106
107
107
107
103
157
156
157
157
156
156
156
157
157
157
157
157
Bus
Cache Line Size (0Ch)
Class Code (09h-0Bh)
CONFIG ENABLE
CONFIG_DATA 0CFCh-0CFFh
Device
Device Identification (02h-03h)
Device Status (06h-07h)
Latency Timer (0Dh)
PCI Arbitration Control 1 (43h)
PCI Arbitration Control 2 (44h)
SDRAM Commands
ACT
MRS
PRE
READ
WRT
SDRAM Initialization Sequence
SDRAM Interface
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