Index (Continued)
Directory Table Entry
Display Controller
73
129–154
135
BT
53
53
53
DR7 and DR6 Bit Definitions
DR7 Register
Buffer Organization
CODEC hardware
129
GD
53
Compression Logic
Compression Technology
CRT Display Modes
Cursor Pattern Memory
DC Memory Organization
130
130
134
136
Gn
LENn
Ln
R/Wn
53
53
53
53
135
DRAM Address Conversion
112
DC_CURSOR_COLOR Register (BX_BASE+8360h) 131
Display FIFO
E
130
131
131
131
135
131
130
135
129
129
133
132
131
136
129
136
139
138
137
137
138
137
138
137
137
138
136
137
137
136
137
137
137
137
136
138
138
137
136
136
137
137
137
137
137
144
EBP register
40
43
43
43
43
43
43
43
43
43
43
43
43
43
43
83
165
182
182
182
182
182
182
183
186
187
185
192
191
193
194
190
182
189
190
190
187
188
193
191
192
74
Display Modes
Display Timing
Dither/Frame-Rate Modulation (FRM)
Graphics Memory Map
Hardware Cursor
Memory Management
Pixel Arrangement Within a DWORD
RAMDAC
EFLAGS Register
Alignment Check Enable (AM)
Auxiliary Carry Flag
Carry Flag
CPUID instruction
Direction Flag (DF)
I/O Privilege Level (IOPL)
Identification Bit
TFT LCD flat panel
Interrupt Enable
TFT Panel Data Bus Formats
TFT Panel Display Modes
VESA-compatible
Nested Task (NT)
Resume Flag (RF)
Sign Flag
VGA Display Support
Trap Enable Flag
Display Controller Block Diagram
Display Controller Registers
Configuration and Status Registers
DC_BORDER_COLOR (8368h-836Bh)
DC_BUF_SIZE (8328h-832Bh)
DC_CB_ST_OFFSET (8314h-8317h)
DC_CFIFO_DIAG (837Ch-837Fh)
DC_CURS_ST_OFFSET (8318h-831Bh)
DC_CURSOR_COLOR (83680h-8363h)
DC_CURSOR_X (8350h-8353h)
DC_CURSOR_Y (8358h-835Bh)
DC_DFIFO_DIAG (8378h-837Bh)
DC_FB_ST_OFFSET (8310h-8313h)
DC_FP_H_TIMING (833Ch-833Fh)
DC_FP_V_TIMING (834Ch-834Fh)
DC_GENERAL_CFG (8304h-8307h)
DC_H_TIMING_1 (8330h-8333h)
DC_H_TIMING_2 (8334h-8337h)
DC_H_TIMING_3 (8338h-833Bh)
DC_LINE_DELTA (8324h-8327h)
DC_OUTPUT_CFG (830Ch-830Fh)
DC_PAL_ADDRESS (8370h-8373h)
DC_PAL_DATA (8374h-8377h)
DC_SS_LINE_CMP (835Ch-835Fh)
DC_TIMING_CFG (8308h-830Bh)
DC_UNLOCK (8300h-8303h)
DC_V_LINE_CNT (8354h-8357h)
DC_V_TIMING_1 (8340h-8343h)
DC_V_TIMING_2 (8344h-8247h)
DC_V_TIMING_3 (8348h-834Bh)
DC_VID_ST_OFFSET (8320h-8323h)
Memory Organization Registers
Display Driver
Virtual 8086 Mode (VM)
EFLAGS register, bit 9
EGA
Electrical Connections
NC-Designated Pins
Power/Ground Connections
Pull-Up/Pull-Down Resisters
Unused Input Pins
Electrical Specifications
Absolute Maximum Ratings
AC Characteristics
Clock Signals
DC Characteristics Table
DCLK Timing
Graphics Port Timing
JTAG AC Specification
JTAG Test Timings
Output Valid Timing
Part Numbers
PCI Interface Signals
SDRAM Interface Signals
Setup and Hold Timings
SYSCLK Timing
System Signals
TCK Timing and Measurement Points
Video Interface Signals
Video Port Timing
Exceptions
Abort
Fault
Trap
75
75
74
234
Extended MMX Instruction Set
Extended MMX™ Instruction Set
Configuration Control Rregister
Legend
BB0_RESET
BB1_RESET
CPU_READ
CPU_WRITE
98
98
98
98
98
98
53
53
53
234
234
F
Scratchpad
Fields - index
207
205
206
207
25
Display Driver Instructions
DR6 Register
Fields - mod and r/m
Fields - sreg3
Fields - ss
Bn
BS
floating point error
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