Electrical Specifications (Continued)
Table 7-10. SDRAM Interface Signals
Symbol
Parameter
Min
Max
Unit
t1
CNTRL* Output Valid from SDCLK[3:0]
Equation Number =
–1.5 (see below)
Equation Number =
–1.0 (see below)
ns
t2
t3
t4
t5
MA[12:0], BA[1:0] Output Valid from
SDCLK[3:0]
Equation Number =
–1.7 (see below)
Equation Number =
–1.2 (see below)
ns
ns
ns
ns
MD[63:0] Output Valid from
SDCLK[3:0]
Equation Number =
–1.6 (see below)
Equation Number =
–0.3 (see below)
MD[63:0] Read Data in Setup to
SDCLKIN
0
MD[63:0] Read Data Hold to SDCLKIN
2.0
*CNTRL = RASA#, RASB# CASA#, CASB#, WEA#, WEB#, CKEA, CKEB, DQM[7:0], CS[3:0]#.
Load = 50pF, Core Vcc = 2.9, I/O Vcc = 3.3V, 25°C.
Output Valid Equation: Use Min or Max number in equation: Min# or Max# + (x * y)
Where: x = shift value applied to SHFTSDCLK field and y = (core clock period) ÷ 2
Note that SHFTSDCLK field = GX_BASE+8404h[5:3], see page 109.
Equation Example:
A 200 MHz GXm processor running a 66 MHz SDRAM bus, with a shift value of 2:
t1 Min = –1.5 + (2 * (5 ÷ 2)) = 3.5 ns
t1 Max = –1.0 + (2 * (5 ÷ 2)) = 4.0 ns
t1, t2, t3
SDCLK[3:0]
CNTRL, MA[12:0],
Valid
BA[1:0], MD[63:0]
Figure 7-6. Output Valid Timing
t5
t7
t4
t6
SDCLKIN
MD[63:0]
Read Data In
Data Valid
Data Valid
Figure 7-7. Setup and Hold Timings - Read Data In
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