Electrical Specifications (Continued)
Table 7-7. Clock Signals
180 MHz (6x)
(Note)
200 MHz (6x)
(Note)
233 MHz (7x)
(Note)
266 MHz (8x)
(Note)
Symbol
ParameterT
Min
Max
Min
Max
Min
Max
Min
Max
Units
t1
t2
t3
t4
t5
t6
t7
t8
t9
SYSCLK Period
33.3
30.0
30.0
30.0
ns
ps
ns
ns
ns
ns
ns
ns
ns
SYSCLK Period Stability
SYSCLK High Time
SYSCLK Low Time
SYSCLK Fall Time
SYSCLK Rise Time
DCLK Period
±250
±250
±250
±250
10
10
10
10
10
10
10
10
0.15
0.15
7.3
2.0
2.0
0.15
0.15
7.3
2.0
2.0
0.15
0.15
7.3
2.0
2.0
0.15
0.15
7.3
2.0
2.0
DCLK Rise/Fall Time
3.0
3.0
17
3.0
16
3.0
13
SDCLK_OUT,
SDCLK[3:0] Period
14.5
7.5
19.5
13
6.5
11
5.5
10
5
t10
t11
t12
t13
SDCLK_OUT,
SDCLK[3:0] High Time
ns
ns
ns
ns
SDCLK_OUT,
SDCLK[3:0] Low Time
7.5
6.5
5.5
5
SDCLK_OUT,
SDCLK[3:0] Fall Time
0.15
0.15
2.0
2.0
0.15
0.15
2.0
2.0
0.15
0.15
2.0
2.0
0.15
0.15
2.0
2.0
SDCLK_OUT,
SDCLK[3:0] Rise Time
Note: SDCLK timings (t9-t13) assume an SDCLK that is a "divide by 3" from the internal core clock. Hence:
180 MHz (6x) = 60.0 MHz SDCLK
200 MHz (6x) = 66.7 MHz SDCLK
233 MHz (7x) = 77.7 MHz SDCLK
266 MHz (8x) = 88.7 MHz SDCLK
t1
t3
V
IH (Min)
1.5V
V
IL (Max)
SYSCLK
t6
t4
t5
Figure 7-1 SYSCLK Timing and Measurement Points
Revision 3.1
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