Processor Programming (Continued)
Table 3-11. Configuration Registers (Continued)
Bit
Name
Description
Index E8h
CCR4 — Configuration Control Register 4 (R/W)
Enable CPUID Instruction:
Default Value = 85h
7
CPUID
If = 1: The ID bit in the EFLAGS register to be modified and execution of the CPUID instruction
occurs as documented in Table 9-2 on page 202.
If = 0: The ID bit can not be modified and execution of the CPUID instruction causes an invalid
opcode exception.
6
5
SMI_NEST
SMI Nest:
If = 1: SMI interrupts can occur during SMM mode. SMI handlers can optionally set SMI_NEST high
to allow higher-priority SMI interrupts while handling the current event
FPU_FAST_EN
FPU Fast Mode Enable:
If = 0: Disable FPU Fast Mode
If = 1: Enable FPU Fast Mode.
4
3
DTE_EN
MEM_BYP
IORT(2:0)
Directory Table Entry Cache:
If = 1: Enables directory table entry to be cached.
Cleared to 0 at reset.
Memory Read Bypassing:
If = 1: Enables memory read bypassing.
Cleared to 0 at reset.
2:0
I/O Recovery Time: Specifies the minimum number of bus clocks between I/O accesses:
000 = No clock delay
001 = 2-clock delay
010 = 4-clock delay
011 = 8-clock delay
100 = 16-clock delay
101 = 32-clock delay (default value after reset)
110 = 64-clock delay
111 = 128-clock delay
Cleared to 0 at reset.
Note: MAPEN (CCR3[4]) must = 1 to read or write to this register.
Index EBh
CCR7 — Configuration Control Register 7 (R/W)
Default Value = 00h
7:3
2
RSVD
NMI
Reserved: Set to 0.
Generate NMI:
0 = Do nothing
1 = Generate NMI
In order to generate multiple NMIs, this bit must be set to zero between each setting of 1.
Reserved: Set to 0.
1
0
RSVD
EMMX
Extended MMX Instructions Enable:
If = 1: extended MMX instructions are enabled
Index 20h
PCR — Performance Control Register (R/W)
Default Value = 07h
7
LSSER
Load/Store Serialize Enable (Reorder Disable): LSSER should be set to ensure that memory-
mapped I/O devices operating outside of the address range 640K to 1M will operate correctly. For
memory accesses above 1 GB, refer to CCR3[7:5] (LSS_34, LSS_23, LSS_12.)
If = 1: All memory read and write operations will occur in execution order (load/store serializing
enabled, reordering disabled).
If = 0: Memory reads and write can be reordered for optimum performance (load/store serializing
disabled, reordering enabled).
Memory accesses in the address range 640K to 1M will always be issued in execution order.
6
5
RSVD
RSVD
RSVD
Reserved: Set to 0.
Reserved: This is a test bit that must be set to 0.
Reserved: Set to 0.
4:0
Note: MAPEN (CCR3[4]) must = 1 to read or write to this register.
Index B0h, B1h, B2h, B3h
SMHR — SMI Header Address Register (R/W)
Default Value = xxh
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