Processor Programming (Continued)
Table 3-10. Configuration Register Map
Register
(Index)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Control Registers
CCR1 (C1h)
RSVD
SMAC
USE_SMI
RSVD
CCR2 (C2h)
CCR3 (C3h)
CCR4 (E8h)
CCR7 (EBh)
PCR (20h)
USE_SUSP
LSS_34
RSVD
WT1
SUSP_HLT
LOCK_NW
RSVD
LSS_23
LSS_12
RSVD
RSVD
MAPEN
DTE_EN
RSVD
NMI_EN
IORT1
RSVD
SMI_LOCK
IORT0
CPUID
SMI_NEST
MEM_BYP
RSVD
IORT2
NMI
EMMX
LSSER
Device ID Registers
DIR0 (FEh)
DIR1 (FFh)
DID3
SID3
DID2
SID2
DID1
SID1
DID0
SID0
RSVD
RID3
CLKMODE1
RID2
RSVD
RID1
CLMODE0
RID0
SMM Base Header Address Registers
SMAR0 (CDh)
SMAR1 (CEh)
SMAR2 (CFh)
SMHR0 (B0h)
SMHR1 (B1h)
SMHR2 (B2h)
SMHR3 (B3h)
A31
A23
A15
A7
A30
A22
A14
A6
A29
A21
A13
A5
A28
A20
A12
A4
A27
A19
SIZE3
A3
A26
A18
SIZE2
A2
A25
A17
SIZE1
A1
A24
A16
SIZE0
A0
A15
A23
A31
A14
A22
A30
A13
A21
A29
A12
A20
A28
A11
A19
A27
A10
A18
A26
A9
A8
A17
A26
A16
A24
Graphics/VGA Related Registers
GCR (B8h)
RSVD
Scratchpad Size
Base Address Code
VGACTL (B9h)
RSVD
Enable SMI Enable SMI Enable SMI
for VGA
memory
B8000h to
BFFFFh
for VGA
memory
B0000h to
B7FFFh
for VGA
memory
A0000h to
AFFFFh
VGAM0 (BAh)
VGAM1 (BBh)
VGAM2 (BCh)
VGAM3 (BDh)
VGA Mask Register Bits [7:0]
VGA Mask Register Bits [15:8]
VGA Mask Register Bits [23:16]
VGA Mask Register Bits [31:24]
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