Processor Programming (Continued)
3.3.2.4 Test Registers
The TLB Test Data Register (TR7) contains the upper 20
bits of the physical address (TLB data field), three LRU
bits and a control bit. During TLB write operations, the
physical address in TR7 is written into the TLB entry
selected by the contents of TR6. During TLB lookup oper-
ations, the TLB data selected by the contents of TR6 is
loaded into TR7. Table 3-15 lists the bit definitions for TR7
and TR6.
The five test registers are used in testing the processor’s
Translation Lookaside Buffer (TLB) and on-chip cache. TR6
and TR7 are used for TLB testing, and TR3-TR5 are used
for cache testing. Table 3-14 is a register map for the Test
Registers with their bit definitions given in Tables 3-15 and
3-17.
TLB Test Registers
The TLB Test Control Register (TR6) contains a com-
mand bit, the upper 20 bits of a linear address, a valid bit
and the attribute bits used in the test operation. The con-
tents of TR6 are used to create the 24-bit TLB tag during
both write and read (TLB lookup) test operations. The
command bit defines whether the test operation is a read
or a write.
The processor’s TLB is a 32-entry, four-way set associa-
tive memory. Each TLB entry consists of a 24-bit tag and
20-bit data. The 24-bit tag represents the high-order 20
bits of the linear address, a valid bit, and three attribute
bits. The 20-bit data portion represents the upper 20 bits
of the physical address that corresponds to the linear
address.
Table 3-14. TLB Test Registers
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
TR7 Register
TLB Test Data Register (R/W)
Physical Address
0
0
TLB LRU
0
0
PL REP
0
0
0
TR6 Register
TLB Test Control Register (R/W)
Linear Address
V
D
D#
U
U#
R
R#
0
0
0
C
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