Electrical Specifications (Continued)
Table 6-16. PCI Interface Signals (Refer to Figures 6-7 and 6-8)
Symbol
Parameter
Min
Max
Unit
Comments
tVAL1
tVAL2
tON
Delay Time, SYSCLK to Signal Valid for Bused Signals
Delay Time, SYSCLK to Signal Valid for GNT#
Delay Time, Float to Active
2
2
2
11
9
ns
ns
ns
ns
ns
ns
ns
Notes 1, 2
tOFF
tSU1
tSU2
tH
Delay Time, Active to Float
28
Input Setup Time for Bused Signals
Input Setup Time for REQ#
7
6
0
Notes 1, 2
Input Hold Time to SYSCLK
Notes: 1. GNT# and REQ# are point-to-point signals. All other PCI interface signals are bused.
Refer to Chapter 4 of PCI Local Bus Specification, Revision 2.1, for more detailed information.
2. Maximum timings are improved over the PCI Local Bus Specification, Revision 2.1. This allows a PAL or
some other circuit to use a REQ/GNT pair to expand the number of REQ/GNT pairs available to the sys-
tem (See application note, “GXLV Processor Series: Request/Grant Pair Expansion”.
SYSCLK
t
VAL1,2
OUTPUT
TRI-STATE®
OUTPUT
t
ON
t
OFF
Figure 6-7. Output Timing
SYSCLK
INPUT
t
t
SU1,2
H
Figure 6-8. Input Timing
Revision 1.1
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