Electrical Specifications (Continued)
Table 6-14. Clock Signals (Refer to Figures 6-5 and 6-6)
SYSCLK = 33 MHz SYSCLK = 30 MHz
Symbol
Parameter
Min
Typ
Max
Min
Typ
Max
Units Comments
t1
t2
t3
t4
t5
t6
t9
SYSCLK Period
29.75
30.0
30.25
±250
33.05
33.3
33.55
±250
ns
ps
ns
ns
ns
ns
Note 1
SYSCLK Period Stability
SYSCLK High Time
SYSCLK Low Time
SYSCLK Fall Time
SYSCLK Rise Time
10.5
10.5
0.5
11.66
11.66
0.5
1.5
1.5
1.5
1.5
Note 3
Note 3
0.5
0.5
SDCLK_OUT, SDCLK[3:0] Period
166 MHz / 2.5
180 MHz / 2.5
180 MHz / 3
200 MHz / 3
233 MHz / 3
233 MHz / 3.5
266 MHz / 3.5
266 MHz / 4
13
15.0
17
ns
ns
ns
Note 2
Note 2
Note 2
11.9
14.7
13.9
16.7
16.9
18.7
13
10.9
13
15.0
12.9
15.0
13.1
15.0
17
15.9
17
11.1
13
16.1
17
t10
SDCLK_OUT, SDCLK[3:0] High Time
166 MHz / 2.5
180 MHz / 2.5
180 MHz / 3
200 MHz / 3
233 MHz / 3
233 MHz / 3.5
266 MHz / 3.5
266 MHz / 4
6.5
5.95
7.35
6.5
5.45
6.5
5.55
6.5
t11
SDCLK_OUT, SDCLK[3:0] Low Time
166 MHz / 2.5
180 MHz / 2.5
180 MHz / 3
200 MHz / 3
233 MHz / 3
233 MHz / 3.5
266 MHz / 3.5
266 MHz / 4
6.5
5.95
7.35
6.5
5.45
6.5
5.55
6.5
Revision 1.1
197
www.national.com
NSC [ National Semiconductor ]
