Electrical Specifications (Continued)
Table 6-18. Video Interface Signals (Refer to Figures 6-11 through 6-13)
Symbol
Parameter
Min
Max
Unit
t1
t2
t3
t4
PCLK Period
6.5
3
40
ns
ns
ns
ns
PCLK High Time
PCLK Low Time
3
PIXEL[17:0], CRT_HSYNC, CRT_VSYNC, FP_HSYNC,
FP_VSYNC, ENA_DISP Valid Delay from PCLK Rising Edge
2
5
t5
VID_CLK Period
8.5
5
ns
ns
ns
ns
ns
ns
%
t6
VID_RDY Setup to VID_CLK Rising Edge
VID_RDY Hold to VID_CLK Rising Edge
VID_VAL, VID_DATA[7:0] Valid Delay from VID_CLK Rising Edge
DCLK Period
t7
2
t8
2
5
t9
6.5
t10
tcyc
DCLK Rise/Fall Time
2
DCLK Duty Cycle
40
60
t1
t4
t2
t3
PCLK
PIXEL[17:0],
CRT_HSYNC, CRT_VSYNC,
FP_HSYNC, FP_VSYNC,
ENA_DISP
Data Valid
Data Valid
Figure 6-11. Graphics Port Timing
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