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30134-23 参数 Datasheet PDF下载

30134-23图片预览
型号: 30134-23
PDF下载: 下载PDF文件 查看货源
内容描述: 的Geode ™ GXLV处理器系列的低功耗X86集成解决方案 [Geode⑩ GXLV Processor Series Low Power Integrated x86 Solutions]
分类和应用: 外围集成电路时钟
文件页数/大小: 247 页 / 4117 K
品牌: NSC [ National Semiconductor ]
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Architecture Overview (Continued)  
1.1 INTEGER UNIT  
1.3 WRITE-BACK CACHE UNIT  
The integer unit consists of:  
The 16 KB write-back unified (data/instruction) cache is  
configured as four-way set associative. The cache stores  
up to 16 KB of code and data in 1024 cache lines.  
Instruction Buffer  
Instruction Fetch  
Instruction Decoder and Execution  
The GXLV processor provides the ability to allocate a por-  
tion of the L1 cache as a scratchpad, which is used to  
accelerate the Virtual Systems Architecture technology  
algorithms as well as for some graphics operations.  
The pipelined integer unit fetches, decodes, and executes  
x86 instructions through the use of a five-stage integer  
pipeline.  
The instruction fetch pipeline stage generates, from the  
1.4 MEMORY MANAGEMENT UNIT  
on-chip cache,  
a continuous high-speed instruction  
stream for use by the processor. Up to 128 bits of code  
are read during a single clock cycle.  
The memory management unit (MMU) translates the lin-  
ear address supplied by the integer unit into a physical  
address to be used by the cache unit and the internal bus  
interface unit. Memory management procedures are x86-  
compatible, adhering to standard paging mechanisms.  
Branch prediction logic within the prefetch unit generates  
a predicted target address for unconditional or conditional  
branch instructions. When  
a branch instruction is  
detected, the instruction fetch stage starts loading instruc-  
tions at the predicted address within a single clock cycle.  
Up to 48 bytes of code are queued prior to the instruction  
decode stage.  
The MMU also contains a load/store unit that is responsi-  
ble for scheduling cache and external memory accesses.  
The load/store unit incorporates two performance-  
enhancing features:  
The instruction decode stage evaluates the code stream  
provided by the instruction fetch stage and determines the  
number of bytes in each instruction and the instruction  
type. Instructions are processed and decoded at a maxi-  
mum rate of one instruction per clock.  
Load-store reordering that gives memory reads  
required by the integer unit a priority over writes to  
external memory.  
Memory-read bypassing that eliminates unnecessary  
memory reads by using valid data from the execution  
unit.  
The address calculation function is pipelined and contains  
two stages, AC1 and AC2. If the instruction refers to a  
memory operand, AC1 calculates  
address for the instruction.  
a linear memory  
1.5 INTERNAL BUS INTERFACE UNIT  
The internal bus interface unit provides a bridge from the  
GXLV processor to the integrated system functions (i.e.,  
memory subsystem, display controller, graphics pipeline)  
and the PCI bus interface.  
The AC2 stage performs any required memory manage-  
ment functions, cache accesses, and register file  
accesses. If a floating point instruction is detected by  
AC2, the instruction is sent to the floating point unit for  
processing.  
When external memory access is required, the physical  
address is calculated by the memory management unit  
and then passed to the internal bus interface unit, which  
translates the cycle to an X-Bus cycle (the X-Bus is a pro-  
prietary internal bus which provides a common interface  
for all of the integrated functions). The X-Bus memory  
cycle is arbitrated between other pending X-Bus memory  
requests to the SDRAM controller before completing.  
The execution stage, under control of microcode, exe-  
cutes instructions using the operands provided by the  
address calculation stage.  
Write-back, the last stage of the integer unit, updates the  
register file within the integer unit or writes to the  
load/store unit within the memory management unit.  
In addition, the internal bus interface unit provides config-  
uration control for up to 20 different regions within system  
memory with separate controls for read access, write  
access, cacheability, and PCI access.  
1.2 FLOATING POINT UNIT  
The floating point unit (FPU) interfaces to the integer unit  
and the cache unit through a 64-bit bus. The FPU is x87-  
instruction-set compatible and adheres to the IEEE-754  
standard. Because almost all applications that contain  
FPU instructions also contain integer instructions, the  
GXLV processor’s FPU achieves high performance by  
completing integer and FPU operations in parallel.  
FPU instructions are dispatched to the pipeline within the  
integer unit. The address calculation stage of the pipeline  
checks for memory management exceptions and  
accesses memory operands for use by the FPU. Once the  
instructions and operands have been provided to the FPU,  
the FPU completes instruction execution independently of  
the integer unit.  
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