Instruction Set (Continued)
8.1.4.2 sreg3 Field (FS and GS Segment Register
Selection)
The sreg3 field (Table 8-12) is 3-bit field that is similar to
the sreg2 field, but allows use of the FS and GS segment
registers.
Table 8-9. General Registers Selected by mod
r/m Fields and w Field
16-Bit
32-Bit
Operation
Operation
mod
r/m
w = 0
w = 1
w = 0
w = 1
Table 8-12. sreg3 Field Encoding
11
11
11
11
11
11
11
11
000
001
010
011
100
101
110
111
AL
CL
DL
BL
AX
CX
DX
BX
SP
BP
SI
AL
CL
DL
BL
AH
CH
DH
BH
EAX
ECX
EDX
EBX
ESP
EBP
ESI
sreg3 Field
Segment Register Selected
000
001
010
011
100
101
110
111
ES
CS
AH
CH
DH
BH
SS
DS
FS
DI
EDI
GS
Undefined
Undefined
8.1.4 reg Field
The reg field (Table 8-10) determines which general regis-
ters are to be used. The selected register is dependent on
whether a 16- or 32-bit operation is current and on the
status of the w bit.
8.1.5 s-i-b Byte (Scale, Indexing, Base)
The s-i-b fields provide scale factor, indexing and a base
field for address selection. The ss, index and base fields
are described next.
Table 8-10. General Registers Selected by reg
Field
8.1.5.1 ss Field (Scale Selection)
The ss field (Table 8-13) specifies the scale factor used in
the offset mechanism for address calculation. The scale
factor multiplies the index value to provide one of the com-
ponents used to calculate the offset address.
16-Bit Operation
32-Bit Operation
reg
w = 0
w = 1
w = 0
w = 1
000
001
010
011
100
101
110
111
AL
CL
DL
BL
AH
CH
DH
BH
AX
CX
DX
BX
SP
BP
SI
AL
CL
DL
BL
EAX
ECX
EDX
EBX
ESP
EBP
ESI
Table 8-13. ss Field Encoding
ss Field
Scale Factor
AH
CH
DH
BH
00
01
01
11
x1
x2
x4
x8
DI
EDI
8.1.4.1 sreg2 Field (ES, CS, SS, DS Register
Selection)
The sreg2 field (Table 8-11) is a 2-bit field that allows one
of the four 286-type segment registers to be specified.
Table 8-11. sreg2 Field Encoding
sreg2 Field
Segment Register Selected
00
01
10
11
ES
CS
SS
DS
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