Instruction Set (Continued)
8.2.1.2 CPUID Instruction with EAX = 00000001h
Standard function 01h (EAX = 1) of the CPUID instruction
returns the processor type, family, model, and stepping
information of the current processor in the EAX register
(see Table 8-18). The EBX and ECX registers are
reserved.
Table 8-19. EDX CPUID Data Returned when
EAX = 1 (Continued)
Returned
Contents*
CR4
Bit
EDX
Feature Flag
Machine Check
EDX[14]
0
-
Architecture
EDX[15]
1
Conditional Move
Instructions
-
Table 8-18. EAX, EBX, ECX CPUID Data
Returned when EAX = 1
EDX[16]
EDX[22:17]
EDX[23]
EDX[24]
0
0
1
0
Page Attribute Table
Reserved
-
-
-
-
Returned
Register
EAX[3:0]
Contents
Description
Stepping ID
MMX Instructions
xx
4
5
0
-
Fast FPU Save and
Restore
EAX[7:4]
EAX[11:8]
EAX[15:12]
EAX[31:16]
EBX
Model
EDX[31:25]
0
Reserved
-
Family
Note: *0 = Not Supported
Type
Reserved
Reserved
Reserved
8.2.1.3 CPUID Instruction with EAX = 00000002h
Standard function 02h (EAX = 02h) of the CPUID instruc-
tion returns information that is specific to the National
Semiconductor family of processors. Information about
the TLB is returned in EAX as shown in Table 8-20. Infor-
mation about the L1 cache is returned in EDX.
-
ECX
-
The standard feature flags supported are returned in the
EDX register as shown in Table 8-19. Each flag refers to a
specific feature and indicates if that feature is present on
the processor. Some of these features have protection
control in CR4. Before using any of these features on the
processor, the software should check the corresponding
feature flag. Attempting to execute an unavailable feature
can cause exceptions and unexpected behavior. For
example, software must check EDX bit 4 before attempt-
ing to use the Time Stamp Counter instruction.
Table 8-20. Standard CPUID with
EAX = 00000002h
Returned
Contents
Register
Description
EAX
xx xx 70 xxh TLB is 32 entry, 4-way set asso-
ciative, and has 4 KB pages.
EAX
xx xx xx 01h The CPUID instruction needs to
be executed only once with an
input value of 02h to retrieve
complete information about the
cache and TLB.
Table 8-19. EDX CPUID Data Returned when
EAX = 1
Returned
Contents*
CR4
Bit
EBX
ECX
EDX
Reserved
Reserved
EDX
EDX[0]
Feature Flag
FPU On-Chip
1
0
0
0
1
1
-
-
xx xx xx 80h L1 cache is 16 KB, 4-way set
associated, and has 16 bytes per
line.
EDX[1]
EDX[2]
EDX[3]
EDX[4]
EDX[5]
Virtual Mode Extension
Debug Extensions
-
Page Size Extensions
Time Stamp Counter
-
2
-
RDMSR / WRMSR
Instructions
EDX[6]
0
Physical Address
Extensions
-
EDX[7]
EDX[8]
EDX[9]
EDX[10]
EDX[11]
0
1
0
0
0
Machine Check Exception
CMPXCHG8B Instruction
On-Chip APIC Hardware
Reserved
-
-
-
-
-
SYSENTER / SYSEXIT
Instructions
EDX[12]
EDX[13]
0
0
Memory Type Range
Registers
-
-
Page Global Enable
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